Anti-Fuse OTP Cell Layout With CPODE Leakage Isolation
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Solution Overview
Problem
Current anti-fuse memory cells have limitations in configuration that result in increased overall cell area and current leakage between adjacent cells, which affects the efficiency and reliability of integrated circuits.
Innovation Solution
The use of a common active region and dummy polysilicon lines, specifically continuous polysilicon lines over active region edges (CPODE), to reduce cell area and minimize current leakage by eliminating gaps between anti-fuse cells and providing electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional anti-fuse cell configuration is used, then cell structure is simple, but overall cell area is large and current leakage occurs between adjacent cells
Solution Approach 1:
The patent divides the cell structure into distinct regions with isolation structures placed between adjacent anti-fuse cells. The isolation structures segment the cell array to prevent current leakage while maintaining individual cell functionality, resolving the contradiction between reducing cell area and preventing current leakage.
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between adjacent anti-fuse cells. These isolation structures act as mediators that block current leakage paths while allowing the cells to remain closely spaced, thus reducing overall cell area without compromising reliability.
2Reliability
If isolation structures are added between cells, then current leakage is reduced, but cell area increases
Solution Approach 1:
The patent applies isolation structures only in specific locations where current leakage occurs between adjacent cells, rather than uniformly across the entire cell array. This localized approach provides current leakage prevention while minimizing the additional area occupied by isolation structures.
Solution Approach 2:
The patent uses minimal isolation structures placed strategically between cells to provide sufficient current leakage prevention. Rather than completely isolating all cells with extensive structures, the partial action of targeted isolation achieves the required reliability with minimal area overhead.
Data Source
AI summary
A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.