Anti-Fuse OTP Cell Layout With Shared Active Region Isolation
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Solution Overview
Problem
Current anti-fuse memory cells have limitations in configuration that result in increased overall cell area and current leakage between adjacent cells, which affects the efficiency and design of integrated circuits.
Innovation Solution
The use of a common active region and dummy polysilicon lines, specifically continuous polysilicon lines over active region edges (CPODE), to reduce cell area while minimizing current leakage by creating a dielectric barrier between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate active regions are used for each anti-fuse cell, then current leakage between cells is reduced, but overall cell area increases
Solution Approach 1:
Multiple adjacent anti-fuse cells share a common active region instead of having separate active regions. This merging of active regions significantly reduces the total cell area while the dummy polysilicon lines provide electrical isolation to prevent current leakage between cells.
Solution Approach 2:
Dummy polysilicon lines are introduced as intermediary structures between adjacent anti-fuse cells. These dummy lines act as barriers that block current leakage paths while allowing the active regions to be shared, thus resolving the contradiction between area reduction and leakage prevention.
2Reliability
If standard anti-fuse cell configuration is used, then cell functionality is maintained, but cell area and current leakage are increased
Solution Approach 1:
Adjacent anti-fuse cells are configured to share common active regions, reducing the total area occupied by the cell array. The dummy polysilicon lines are strategically placed to maintain proper electrical isolation and cell functionality despite the merged active regions.
Solution Approach 2:
The cell structure is modified locally by adding dummy polysilicon lines at specific positions between adjacent cells. These local modifications provide the necessary electrical isolation and maintain cell functionality without requiring complete restructuring of the entire cell array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall cell area by approximately 34-45% and minimizes current leakage between anti-fuse cells, enhancing the design efficiency of anti-fuse cell arrays.
Implementation Method 1
minimizing current leakage by creating a dielectric barrier between adjacent cells
Data Source
AI summary
A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.