OTP Block in Flash Memory Array for SoC Security
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Solution Overview
Problem
System-on-Chip (SoC) security faces challenges in implementing one-time programmable (OTP) memory due to the inability of flash memory to be used for security functions, as it can be erased, increasing costs and complexity when OTP is added, and existing solutions fail to securely prevent unauthorized modifications.
Innovation Solution
Implementing a flash memory array with an OTP block that includes a write inhibit field, using a controller and flash memory controller to latch data in volatile memory upon power cycling, and employing an OTP state machine to enforce the OTP nature of the block, ensuring it cannot be modified or erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If flash memory is used for security functions, then cost and area are reduced, but security is compromised because flash memory can be erased
Solution Approach 1:
The flash memory array is segmented into a regular flash memory portion and a dedicated OTP block portion. The OTP block within the flash array is configured to be non-erasable while the rest of the flash memory retains erasable functionality. This segmentation allows the system to use flash memory technology while providing a secure non-erasable region for security functions.
Solution Approach 2:
Different regions of the flash memory array are assigned different properties: the OTP block has non-erasable properties while the rest of the array has erasable properties. This is achieved through specific page programming and erasure control where only non-OTP pages can be erased, while OTP pages remain protected from erasure operations.
2Reliability
If OTP memory is added to SoC for security functions, then security is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The OTP block is merged with the flash memory array to form an integrated structure. The OTP block shares the same physical memory array, control logic, and interface circuitry as the regular flash memory, eliminating the need for separate OTP memory hardware. This combining reduces device complexity while maintaining security functionality.
Solution Approach 2:
The flash memory controller is designed to handle both regular flash memory operations and OTP block operations through a unified interface. The same controller can perform page programming, page erasure on non-OTP blocks, and read operations on both OTP and non-OTP regions, reducing the need for additional dedicated control circuitry.
3Area of stationary object
If OTP block is implemented within flash memory array, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the logical and operational parameters of the flash memory array to create the OTP block, rather than requiring different physical manufacturing parameters. By using specific page programming operations and erasure protection mechanisms, the same flash memory cells can exhibit different behavioral characteristics (erasable vs. non-erasable) based on their configuration rather than physical structure.
Data Source
AI summary
System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.