Anti-Fuse OTP Memory Array Using Isolation Transistors
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Solution Overview
Problem
The anti-fuse type one-time programmable (OTP) memory device faces challenges in downscaling due to the insulating structures required for isolation between unit cells, which hinder memory density and introduce stress effects during fabrication.
Innovation Solution
The implementation of isolation transistors, rather than traditional isolation structures, between adjacent unit cells in the anti-fuse OTP memory array, allows for effective electrical isolation while reducing the overall footprint and minimizing stress effects, thereby enhancing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating structures are used for isolation between unit cells, then electrical isolation is achieved, but memory density is reduced and stress effects are introduced
Solution Approach 1:
The patent introduces isolation transistors as intermediary elements between adjacent unit cells. These transistors act as controllable switches that can block current flow between cells when in the off state, providing electrical isolation without requiring physical insulating structures. The isolation transistor includes a gate electrode, source electrode, and drain electrode positioned between adjacent bit lines, creating a controllable barrier that replaces traditional insulating materials.
2Reliability
If insulating structures are used for isolation between unit cells, then electrical isolation is achieved, but stress effects on unit cells increase
Solution Approach 1:
The patent replaces the mechanical/physical isolation approach (using insulating structures) with an electrical control approach (using isolation transistors). Instead of relying on physical barriers that can introduce mechanical stress during fabrication and operation, the invention uses electrically controllable transistors that can be turned on or off to achieve isolation. This substitution eliminates the stress effects associated with rigid insulating structures while maintaining effective electrical isolation between unit cells.
3Reliability
If traditional isolation structures are used, then unit cell isolation is achieved, but device footprint increases
Solution Approach 1:
The patent merges the isolation function with the existing transistor structure by using isolation transistors that share the same fabrication process and structural elements as the access transistors in each unit cell. The isolation transistors utilize the same gate electrode, source/drain electrode configurations, and interconnect layers, consolidating multiple functions into a unified structure. This merging approach reduces the overall device footprint by eliminating separate isolation structures and optimizing the use of available space between adjacent unit cells.
Data Source
AI summary
The present application provides an anti-fuse one-time programmable (OTP) memory array and a manufacturing method of the anti-fuse one-time programmable (OTP) memory array. The memory array includes: active areas; pairs of programming word lines and read word lines; and dummy word lines. The active areas extend along a first direction in a semiconductor substrate, and are separately arranged along a second direction. The programming word lines, the read word lines and the dummy word lines extend along the second direction over the semiconductor substrate. A region in which a pair of programming word line and read word line are intersected with one of the active areas defines a unit cell in the memory array. The dummy word lines respectively lie between adjacent pairs of programming word lines and read word lines. A region in which one of the dummy word lines is intersected with one of the active areas defines an isolation transistor.