OTP Memory Access Circuit Simultaneous Write Segmentation
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Solution Overview
Problem
One-time programmable (OTP) memory devices face limitations in write performance, as they are typically irreversible and require programming after manufacturing, which can lead to inefficiencies in data storage and retrieval within semiconductor memory devices.
Innovation Solution
The OTP memory device incorporates a memory cell array with both main and dummy cells, where the access circuit allows for simultaneous writing to multiple main cells during a single write time by activating multiple word lines and selecting corresponding bit lines, enhancing write performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OTP memory is programmed by breaking fuse connection or creating antifuse connection, then data storage reliability is improved, but write time and manufacturing cost increase
Solution Approach 1:
The memory cell array is divided into multiple main cell groups (first main cell group, second main cell group, etc.) with each group containing multiple main cells. This segmentation allows the access circuit to simultaneously write data to multiple different main cells across different cell groups during a single write operation, thereby reducing total write time while maintaining the reliable OTP programming mechanism in each cell
Solution Approach 2:
Multiple write operations that would traditionally occur sequentially are merged into a single simultaneous write operation. The access circuit activates multiple word lines and selects multiple bit lines to write data to multiple main cells at the same time, combining multiple programming actions into one unified operation that reduces overall write time
2Adaptability or versatility
If OTP memory is programmed after manufacturing, then adaptability to end use is improved, but manufacturing cost and testing time increase
Solution Approach 1:
The patent introduces dummy cells that are configured identically to main cells but are not intended for data storage. These dummy cells are prepared in advance during manufacturing and can be used for testing and validation purposes before the actual OTP programming of main cells occurs after manufacturing, thereby reducing post-manufacturing testing time and cost
3Speed
If multiple word lines are activated simultaneously for writing, then write speed is improved, but circuit complexity increases
Solution Approach 1:
The memory array is segmented into multiple main cell groups that can be independently accessed. Each cell group can be activated through its own word lines, allowing the access circuit to selectively activate only the necessary cell groups for each write operation. This segmentation manages circuit complexity by organizing the memory structure into manageable, independently controllable units
Data Source
AI summary
A one-time programmable (OTP) memory device includes an OTP memory cell array comprising a plurality of dummy cells and a plurality of main cell groups of main cells and an access circuit configured to write data to at least two of the cells simultaneously. The arrangement of the dummy cells and the main cell groups may allow for the reliable writing of multi-bit data to the memory array. Each of the main cell groups may include a plurality of main cells which are connected to word lines, respectively, and to bit lines, respectively. Each of the main cells may be writable and each of the dummy cells may be unwritable. Each of the main cells may include a contact layer, and the dummy cells might not include the contact layer. A supply voltage may be applied to the OTP memory cell array through the contact layer.