One-Time Programmable Memory With Anti-Fuse Error Correction
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Solution Overview
Problem
Conventional one-time programmable (OTP) memories lack a correction function, requiring redundant storage bits and circuits to correct programming errors, which increases manufacturing costs and complicates circuit design.
Innovation Solution
A modifiable OTP memory design incorporating an electric fuse structure, an anti-fuse transistor, and a word select transistor, allowing for secondary programming to correct resistance levels and omit redundant storage bits and circuits, using distinct program voltages for each programming state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant storage bits and circuits are added to correct programming errors, then the correction function is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The OTP memory cell is designed to perform both normal storage function and error correction function through the same basic circuit structure. By utilizing the anti-fuse transistor in parallel with the electric fuse structure, the same memory cell can store data normally and also correct programming errors when needed, eliminating the need for separate redundant circuits.
Solution Approach 2:
The invention changes the resistance parameters of the memory cell by applying different voltages. During normal operation, the cell operates with standard voltage levels. During error correction, a higher voltage (Vpp) is applied to blow the anti-fuse transistor, changing the resistance state to correct the error. This parameter-based approach allows function switching without additional hardware.
2Reliability
If redundant storage bits and circuits are added to correct programming errors, then the correction function is improved, but the manufacturing cost increases
Solution Approach 1:
The same OTP memory cell structure serves dual purposes: normal data storage and error correction. This eliminates the need for separate redundant storage bits and correction circuits, reducing the total component count and manufacturing cost while maintaining the correction function.
Solution Approach 2:
The invention merges the error correction functionality into the existing memory cell structure by adding an anti-fuse transistor in parallel with the electric fuse. This consolidation integrates multiple functions into a single unified structure, reducing manufacturing complexity and cost compared to having separate redundant systems.
3Reliability
If the fuse blowing process is made irreversible for stable data storage, then the data reliability is improved, but the adaptability for correction operations deteriorates
Solution Approach 1:
The invention segments the memory structure into two independent components: an electric fuse structure for normal irreversible data storage, and an anti-fuse transistor for correction operations. The electric fuse provides stable, irreversible storage while the anti-fuse transistor can be selectively blown to correct errors, allowing both data stability and correction capability to coexist through structural segmentation.
Solution Approach 2:
The anti-fuse transistor acts as an intermediary correction mechanism that operates in parallel with the main electric fuse structure. It provides a controlled way to modify the memory state when errors occur, while the primary electric fuse maintains its irreversible stable storage function. The intermediary structure enables correction without compromising the fundamental stability of the storage system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables direct correction of programming errors through secondary programming, simplifying circuit design, reducing manufacturing costs, and enhancing flexibility and reliability while maintaining data reliability.
Implementation Method 1
a fuse mostly refers to an electric fuse (eFuse) based on metal electro-migration (EM) characteristics, and the electric fuse is blown to change its resistance value between two ends of the eFuse (from small to large)
Implementation Method 2
A polysilicon based anti-fuse refers to a device in which the resistance between the polysilicon layer and a N+ diffusion layer is changed (from large to small) by breaking down the isolation layer between the two layers
Data Source
AI summary
A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.