OTP Memory Bit Cell with Shared Word Line and Multiple Antifuse Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
One-time programmable (OTP) memory devices with a two-transistor per bit arrangement face challenges in reading cell current due to small cell current and difficulties in placing vertical interconnects on active regions and gate strips to connect metal tracks for bit line and word line signals.
Innovation Solution
Implementing multiple OTP memory cells per bit cell, sharing a word line and bit line, which increases cell current readability and flexibility in via placement for signal connections, using a combination of antifuse and selection transistors with thinner gate dielectric layers for programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a two-transistor per bit arrangement is used in OTP memory, then the device structure is simple, but the cell current is small and difficult to read
Solution Approach 1:
The patent divides the bit cell into multiple independent OTP memory cells (first OTP memory cell and second OTP memory cell) that share common word lines and bit lines. Each OTP memory cell contains its own antifuse transistor and selection transistor, allowing independent operation and current contribution to the total readable current while maintaining a systematic structured arrangement.
2Device complexity
If a two-transistor per bit arrangement is used in OTP memory, then the device structure is simple, but vertical interconnect placement is difficult
Solution Approach 1:
The patent merges multiple OTP memory cells into a single bit cell unit that shares common word lines and bit lines. This consolidation allows multiple transistors to be integrated within a compact footprint, providing flexibility in via placement and interconnect routing while maintaining a unified structural organization that simplifies manufacturing.
3Measurement precision
If multiple OTP memory cells share word line and bit line, then cell current readability increases, but device complexity increases
Solution Approach 1:
The patent designs a universal bit cell structure where multiple OTP memory cells share common word lines and bit lines. This multi-functional arrangement allows the same word line and bit line to serve multiple cells simultaneously, increasing the total readable current through parallel contribution while using a standardized shared architecture that manages complexity through reuse rather than duplication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multiple OTP cells per bit arrangement enhances readability by increasing cell current and simplifies the layout, allowing for easier integration of metal tracks, thereby improving the overall performance and efficiency of OTP memory devices.
Implementation Method 1
The gate dielectric layer has a thickness that is lower than a regular gate dielectric layer thickness. The antifuse transistor is programmed by causing a dielectric breakdown at the thin gate dielectric layer.
Implementation Method 2
An antifuse is programmed by electrically shorting the gate and source of a transistor with an dielectric breakdown when a high voltage is applied to the thin gate dielectric layer of the transistor.
Data Source
AI summary
A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.