OTP Memory Bit Locking via Register Control

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Solution Overview

Problem

Conventional memory systems, particularly one-time-programmable (OTP) memory, lack effective mechanisms to securely lock programmed bits, making them vulnerable to tampering and requiring physical replacement for updates, which is inefficient and insecure.

Innovation Solution

A method and system for processing multi-stage programming (MSP) bits within OTP memory, where a register bit associated with each MSP memory bit determines whether to allow or block programming, ensuring that once a bit is programmed, it cannot be altered, using a state machine to manage programming states and prevent re-programming attempts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ROM is utilized to store configuration information, then data security is improved, but adaptability deteriorates as the ROM has to be physically removed and replaced for updates

Engineering Contradiction:
Improvedata securityVSAvoidupdate capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory is segmented into OTP memory cells and associated lock bits, where each lock bit independently controls access to corresponding OTP cells. This segmentation allows selective programming and locking of individual bits, enabling both security and flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from static ROM to dynamic OTP memory with controllable lock bits. The lock bits can be programmed or cleared based on operational conditions, allowing the memory to dynamically change from locked to unlocked state for updates when needed.

Inventive Principle:
Principle #15Dynamics

2Reliability

If OTP memory is used to prevent tampering, then reliability is improved, but device complexity increases due to the need for lock mechanisms

Engineering Contradiction:
Improvetamper resistanceVSAvoidlocking mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The lock functionality is merged with the existing OTP memory structure by using spare bits within the same memory array as lock bits. This integration eliminates the need for separate lock mechanism hardware, reducing overall device complexity while maintaining security.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The OTP memory cells serve dual purposes: storing configuration data and functioning as lock bits for security. Each OTP cell can be used for data storage or as a lock bit depending on programming, providing multi-functionality without additional components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If physical replacement is required for ROM updates, then security is improved, but productivity deteriorates due to time-consuming replacement processes

Engineering Contradiction:
ImprovesecurityVSAvoidupdate speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The mechanical process of physically removing and replacing ROM chips is replaced with an electrical programming process. Lock bits can be programmed or cleared electronically through programming circuits, eliminating the need for physical intervention and enabling rapid updates.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Instead of physically replacing the entire ROM, the system allows selective programming of individual lock bits and OTP cells. This copying approach enables updating specific configuration data without replacing the entire memory device, significantly improving update efficiency.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8032727B2Method and system for locking OTP memory bits after programming
Publication Date: 2011.10.04 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8032727B2 patent drawing
  • US8032727B2 patent drawing
  • US8032727B2 patent drawing

AI summary

Methods and systems for processing multi-stage programming (MSP) bits within one-time-programmable (OTP) memory are disclosed herein. Aspects of the method may comprise determining whether at least one MSP memory bit in the OTP memory is programmed and whether a register bit associated with said at least one MSP memory bit is asserted. If the register bit is deasserted and the MSP memory bit is unprogrammed, the MSP memory bit may be programmed. The register bit in the OTP memory may be associated with the MSP memory bit. The MSP memory bit may be programmed to logic zero or logic one. If the register bit associated with the MSP memory bit is asserted, programming of the MSP memory bit may be blocked. The register bit associated with the MSP memory bit may be reset and it may be determined whether the MSP memory bit is accessed.