One-time Programmable Memory Low Power Read Sensing
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Solution Overview
Problem
Conventional sensing methods for programmable resistive device memories require high supply voltage and current to convert resistance into logic states, making it difficult to operate under low voltage and low current conditions, especially in IoT applications.
Innovation Solution
The proposed solution involves a low power sensing circuit that uses capacitors to discharge through programmable resistive elements, converting resistance into time delays, and comparing these delays with a reference to determine logic states, allowing for ultra-low current operation without relying on high MOS device threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional voltage sense amplifier is used to sense PRE resistance, then resistance can be converted into voltage signal, but high supply voltage and high current are required which increases power consumption
Solution Approach 1:
The patent replaces the conventional voltage-based sensing mechanism with a time-based sensing mechanism. Instead of using voltage amplification to sense resistance, the system uses capacitor discharge time measurement. The sensing circuit measures the time constant (τ = R × C) of capacitor discharge through the programmable resistive element, converting resistance measurement into a time measurement problem, thereby eliminating the need for high-voltage MOS amplifiers and reducing power consumption significantly.
Solution Approach 2:
The patent changes the sensing parameter from voltage to time. By measuring the discharge time of a capacitor through the resistive element rather than the voltage level, the system transforms the resistance sensing task into a time measurement task. This parameter change allows the use of simple timing circuits instead of complex voltage amplification circuits, achieving low-power operation while maintaining sensing accuracy.
2Power
If MOS devices are biased in high gain region for voltage amplification, then voltage signal can be enlarged, but substantial current is required which increases power consumption
Solution Approach 1:
The patent eliminates the need for voltage amplification by substituting it with a time measurement approach. Instead of using high-gain MOS amplifiers to boost voltage signals, the system measures the time constant of capacitor discharge directly. This substitution removes the requirement for biasing MOS devices in high-gain region, thereby eliminating the substantial bias current consumption associated with such amplifiers.
3Reliability
If high voltage is applied to programming OTP element, then element can be programmed into high or low resistance state, but high current flows through element which may cause damage
Solution Approach 1:
The patent employs dynamic voltage programming with multiple voltage levels. Instead of using a single high voltage for programming, the system applies a sequence of voltage levels (e.g., V1, V2, V3) to progressively program the OTP element. This dynamic approach allows the element to be programmed through incremental changes, reducing the peak current stress on the element while maintaining reliable programming capability. The sensing operation later uses low voltage to read the programmed state without causing damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient sensing of programmable resistive device memories at low supply voltages and currents, reducing power consumption while maintaining accurate resistance conversion, suitable for applications like IoT devices.
Implementation Method 1
a capacitor (51) coupled to a supply voltage (VDD) through a charging pass gate (102) and coupled to ground through a discharging pass gate (106). The capacitor (51) is also coupled to a programmable resistive device (103) through the discharging pass gate (106).
Implementation Method 2
The resistance of a PRE in a PRD device needs to be converted into a logic level after reading the PRD cell.
Data Source
AI summary
An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.