OTP Memory Cell Three-State Storage via Oxide Breakdown
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory cell configurations for IC devices are complex and costly, requiring dedicated testing equipment and only allow for two-state data storage, which hinders the adoption of standard foundry processes and increases production costs and time-to-market.
Innovation Solution
A new OTP memory cell design utilizing a thin oxide layer with etch undercut configurations to induce breakdown and change conductivity states, enabling three-state data storage through the use of alternating operational characteristics of conductive polysilicon segments and a dielectric layer that transitions from non-conductive to conductive, facilitating standard IC manufacturing processes and reduced trimming requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional OTP memory cell configurations are used, then two-state data storage is achieved, but device complexity and production cost increase
Solution Approach 1:
The patent changes the operational parameters of the memory cell by utilizing breakdown voltage characteristics to create three distinct resistance states (high resistance, intermediate resistance, and low resistance) instead of conventional two states. This allows encoding of 2 bits per cell through voltage threshold detection, effectively doubling the storage capacity without increasing physical cell complexity
Solution Approach 2:
The invention introduces a voltage threshold dimension for data encoding, where data is stored not only in resistance magnitude but also in voltage threshold characteristics. This additional dimension enables 3-state operation and 2-bit storage per cell while maintaining the same physical memory cell structure
2Reliability
If dedicated testing equipment is used for fuse trimming, then device features are achieved, but productivity decreases and time-to-market increases
Solution Approach 1:
The memory cell structure is designed to be self-testable through standard IC testing equipment. The breakdown voltage characteristics and resistance states can be detected using conventional voltage application and current measurement, eliminating the need for specialized high-current fuse trimming equipment and enabling standard foundry process integration
Solution Approach 2:
The patent designs the memory cell to serve multiple functions: data storage, self-testing, and standard IC process compatibility. The same structure that stores data also provides testable characteristics through its breakdown voltage and resistance properties, allowing a single device to fulfill both storage and testing requirements without additional dedicated equipment
3Loss of information
If conventional OTP memory cells are used, then two-state storage is achieved, but area utilization efficiency decreases
Solution Approach 1:
By changing from two-state to three-state operation through breakdown voltage characteristics, the patent enables 2 bits of information to be stored in each physical memory cell location. This parameter change effectively doubles the information density without requiring additional semiconductor area, as each cell now encodes more information through voltage threshold detection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for higher utilization of OTP memory cells by enabling three-state data storage within the same semiconductor area, reducing production costs and time-to-market by simplifying the manufacturing and testing processes, while maintaining the required device features.
Implementation Method 1
utilizing a thin oxide layer with etch undercut configurations to induce breakdown and change conductivity states
Implementation Method 2
one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer
Data Source
AI summary
A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.