OTP Memory Cell With Dual Fuse Regions And Isolation Layer
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Solution Overview
Problem
Anti-fuse OTP memory devices face issues with blowing failures and defects due to uneven fuse region blowing, leading to reduced yield and read operation errors, especially when the center portion of the fuse region is blown instead of the edge portion.
Innovation Solution
The proposed OTP memory cell design includes two fuse regions with an intermediate isolation layer and a gate electrode having projection portions, which increases the likelihood of successful blowing and prevents defects by ensuring that either fuse can be blown independently, even if one is defective, and the isolation layer extends further towards the well tap to reduce voltage transfer issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two fuse regions are provided in the unit cell to improve blowing yield, then the reliability of programming is improved, but the complexity of the device structure increases
Solution Approach 1:
The gate insulating layer is segmented into two distinct fuse regions (first fuse region and second fuse region) within a single unit cell. This segmentation allows independent blowing of each fuse region, providing redundancy for programming operations while maintaining a relatively compact structure shared with the gate electrode and junction regions.
Solution Approach 2:
The gate electrode structure serves multiple functions: it acts as the control electrode for the transistor operation and simultaneously serves as the programming mechanism for both fuse regions. The gate insulating layer functions both as the dielectric for transistor operation and as the medium containing both fuse regions for programming, reducing the need for separate dedicated structures.
2Reliability
If the isolation layer extends further towards the well tap to prevent voltage transfer issues, then the programming reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
An isolation layer is introduced as an intermediary element positioned between the first fuse region and the well tap. This isolation layer acts as a barrier to prevent unwanted voltage transfer or electrical interference from the well tap to the first fuse region, thereby improving programming reliability. The isolation layer is formed as part of the gate insulating layer structure, integrating the isolation function with the existing transistor gate structure.
3Productivity
If projection portions are added to the gate electrode to increase blowing likelihood, then the programming yield is improved, but the device complexity increases
Solution Approach 1:
The gate electrode is designed with projection portions that extend over specific regions of the gate insulating layer. These projection portions create localized areas with different electrical field distributions, increasing the likelihood of successful blowing in the fuse regions beneath them. The projection portions are strategically positioned to correspond with the first and second fuse regions, providing enhanced programming capability without requiring complete restructuring of the gate electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the blowing yield and prevents defects during read operations by ensuring that either fuse can be successfully blown, reducing the likelihood of resistance value exceeding readable ranges and improving overall cell reliability.
Implementation Method 1
applying a write voltage to the gate electrode, which causes the insulation state of the fuse region to be blown
Implementation Method 2
the fuse poly (fuse region) and a lower well may form a reverse-biased diode
Data Source
AI summary
A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.