Three-Transistor OTP Memory Cell Layout Symmetry

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Solution Overview

Problem

OTP memory cells exhibit variability in programmed connection quality due to layout-dependent effects and physical variations, leading to inconsistent post-programmed resistance and reading challenges.

Innovation Solution

A three-transistor OTP memory cell design is introduced, featuring two pass transistors symmetrically located with respect to a programming MOSFET, enhancing programmability by improving physical uniformity and distribution of programmed cell read current through controlled voltage differentials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional two-transistor OTP memory cell design is used, then the device complexity is lower, but the manufacturing precision and uniformity of programmed connection quality deteriorate due to layout-dependent effects

Engineering Contradiction:

Improveuniformity of programmed connection qualityVSAvoidnumber of transistors in memory cell

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The memory cell is segmented into three distinct transistor components: a programming MOSFET and two pass transistors. This segmentation allows each transistor to be independently optimized and positioned to minimize layout-dependent effects, thereby improving manufacturing precision and uniformity of programmed connection quality while managing device complexity through functional specialization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements symmetric local quality by positioning two pass transistors symmetrically with respect to the programming MOSFET. This symmetric arrangement ensures that both pass transistors experience identical layout conditions and electrical characteristics, eliminating variability caused by asymmetric positioning and improving overall manufacturing precision.

Inventive Principle:

Principle #3Local quality

2Reliability

If physical variations in OTP memory cells are present, then the device complexity remains the same, but the reliability of reading memory cell state deteriorates due to inconsistent post-programmed resistance

Engineering Contradiction:

Improveconsistency of memory cell read currentVSAvoidphysical uniformity of memory cells

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The symmetric positioning of the two pass transistors relative to the programming MOSFET ensures that both transistors experience identical physical conditions and electrical characteristics. This local quality symmetry compensates for physical variations in the memory cell array, improving the reliability and consistency of memory cell read current across different locations.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The two pass transistors are configured to provide equipotential conditions during programming and reading operations. By ensuring that both pass transistors have matched electrical characteristics and are positioned symmetrically, the design equalizes the electrical potential distribution across the memory cell array, reducing variability in post-programmed resistance and improving read reliability.

Inventive Principle:

Principle #12Equipotentiality

3Productivity

If programming efficiency is increased through higher voltage differentials, then the productivity improves, but the reliability may deteriorate due to increased variability in gate oxide breakdown

Engineering Contradiction:

Improveprogramming speedVSAvoiduniformity of gate oxide breakdown

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The symmetric arrangement of the two pass transistors ensures that voltage differentials are applied uniformly during programming operations. This local quality symmetry ensures that gate oxide breakdown occurs consistently across both transistors, maintaining reliability even when high voltage differentials are used to improve programming speed and productivity.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The three-transistor design achieves more uniform gate oxide breakdown and increased programming efficiency, reducing variability and enhancing the reliability of reading memory cell states, with improved conductivity and reduced programming time.

Implementation Method 1

driving the gate electrode to a second voltage to create a high voltage differential between the gate electrode and the two source/drain regions

Methodology Applied

Scientific EffectHigh voltage differential: Electric Field

Implementation Method 2

The memory cell may include one or more select devices, such as a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistors), or a diode, such as a gated diode, to enable selective programming, the rupturing of the dielectric layer for an electrical connection

Methodology Applied

Scientific EffectDielectric breakdown: Antifuse

Data Source

PatentUS10032522B2Three-transistor OTP memory cell

Publication Date: 2018.07.24 SYNOPSYS INC

AI summary

An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.