OTP Memory Cell Pairing for Writing Reliability
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Solution Overview
Problem
Existing one-time programmable (OTP) memory devices using gate insulating film destruction type nonvolatile memory cells face issues with data writing reliability due to deterioration over time, leading to potential read failures, especially when both memory cells in a pair are in a writing deficiency state, causing good products to be determined as bad after shipment.
Innovation Solution
A semiconductor device design that stores one-bit data across two nonvolatile memory cells, allowing simultaneous writing and reading, with verification performed individually on each cell to ensure data integrity, using a drive circuit to manage word lines and a write/read circuit to manage bit lines, ensuring data is correctly written before determining product quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If writing of data is performed simultaneously for two nonvolatile memory cells, then productivity is improved, but reliability deteriorates due to writing deficiency states that may pass verification initially but fail after deterioration
Solution Approach 1:
The verification process is segmented into two distinct phases: simultaneous verification of both memory cells for productivity, followed by individual verification of each cell for reliability. This segmentation allows the system to capture the efficiency of parallel processing while ensuring the rigor of individual cell validation, thereby resolving the contradiction between writing speed and data retention reliability.
Solution Approach 2:
The patent performs a preliminary simultaneous verification of both memory cells after writing, followed by individual verification of each cell. This preliminary action ensures that any writing deficiency states are detected before the product is shipped, preventing future read failures while maintaining the productivity benefits of simultaneous writing operations.
2Productivity
If verification is performed simultaneously for two nonvolatile memory cells, then productivity is improved, but reliability deteriorates because writing deficiency states cannot be detected
Solution Approach 1:
The verification process is segmented into two distinct phases: simultaneous verification of both memory cells for productivity, followed by individual verification of each cell for reliability. This segmentation allows the system to capture the efficiency of parallel processing while ensuring the rigor of individual cell validation, thereby resolving the contradiction between writing speed and data retention reliability.
Solution Approach 2:
The patent performs a preliminary simultaneous verification of both memory cells after writing, followed by individual verification of each cell. This preliminary action ensures that any writing deficiency states are detected before the product is shipped, preventing future read failures while maintaining the productivity benefits of simultaneous writing operations.
3Reliability
If individual verification is performed for each nonvolatile memory cell, then reliability is improved, but productivity deteriorates due to increased process time
Solution Approach 1:
The verification process is segmented into two distinct phases: simultaneous verification of both memory cells for productivity, followed by individual verification of each cell for reliability. This segmentation allows the system to capture the efficiency of parallel processing while ensuring the rigor of individual cell validation, thereby resolving the contradiction between writing speed and data retention reliability.
Solution Approach 2:
The patent performs a preliminary simultaneous verification of both memory cells after writing, followed by individual verification of each cell. This preliminary action ensures that any writing deficiency states are detected before the product is shipped, preventing future read failures while maintaining the productivity benefits of simultaneous writing operations.
4Device complexity
If one-bit data is stored in a single nonvolatile memory cell, then device complexity is reduced, but reliability deteriorates due to susceptibility to deterioration over time
Solution Approach 1:
The patent merges two nonvolatile memory cells to store a single one-bit data, creating a redundant storage system. This merging approach allows the data to be written simultaneously to both cells while enabling individual verification of each cell, thereby improving data retention reliability without significantly increasing device complexity.
Solution Approach 2:
The patent applies different verification strategies to different memory cells: simultaneous verification for both cells to maintain productivity, and individual verification for each cell to ensure reliability. This local quality approach ensures that each cell receives the appropriate level of verification based on its role in the redundant storage system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data reliability by reducing the likelihood of read failures and maintaining low costs, as only products with sufficient data written in both cells are determined as good, allowing for additional writing if verification fails, thus improving overall product reliability without significantly increasing the writing process time.
Implementation Method 1
In the gate insulating film destruction type nonvolatile memory cell, a high voltage is applied on a gate insulating film of a field effect transistor and the gate insulating film is destroyed to thereby enable writing of data
Implementation Method 2
a drive circuit configured to drive a plurality of word lines to select nonvolatile memory cells of the plurality of gate insulating film destruction type nonvolatile memory cells
Implementation Method 3
a write/read circuit where a plurality of bit lines to input and output the data for the selected nonvolatile memory cells are connected
Data Source
AI summary
In an OTP memory storing a one-bit of the data by two gate insulating film destruction type nonvolatile memory cells where a same bit line is connected and different word lines are connected, writings and readings of the data for selected two nonvolatile memory cells constituting one-bit are performed by simultaneously selecting the selected two nonvolatile memory cells, and verifications for the selected two nonvolatile memory cells are performed by individually selecting one and the other of the selected two nonvolatile memory cells one by one.