OTP Memory Layout Using Dielectric Breakdown for Smaller Bit Cells
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory elements in integrated circuits (ICs) require high current for programming operations, leading to larger bit cell sizes due to the need for fusing metal lines during programming.
Innovation Solution
An IC device configuration with parallel metal lines separated by a dielectric layer, where an operational voltage creates a breakdown path through the dielectric layer, allowing for programming with less current, using transistors with smaller channel sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high current is used for programming operations in OTP memory elements, then programming can be achieved through metal line fusing, but the bit cell size increases
Solution Approach 1:
The patent changes the programming mechanism from high-current metal line fusing to low-current dielectric breakdown. By applying a high voltage (e.g., 5V) across the dielectric layer between two metal lines, a localized breakdown path is created that serves as the programming mechanism, thereby reducing the current requirement and allowing for smaller bit cell sizes
Solution Approach 2:
The patent replaces the mechanical/thermal fusing process with an electrical field-based dielectric breakdown mechanism. Instead of using high current to melt and fuse metal lines, the invention uses a high voltage electric field to create a controlled breakdown path through the dielectric layer, achieving programming with lower current and reduced bit cell area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces overall bit cell size by minimizing current requirements during programming operations, enabling smaller transistors and more efficient OTP memory elements.
Implementation Method 1
The operational voltage has a programming magnitude sufficiently large to create a breakdown path through the dielectric layer
Data Source
AI summary
An integrated circuit (IC) device includes a gate via, a drain via, a first metal line in a first metal layer of the IC device, overlying and electrically connected to the gate via, and configured to receive an operational voltage, a second metal line in the first metal layer parallel to and adjacent to the first metal line and overlying and electrically connected to the drain via, and a transistor including a source terminal coupled to a reference voltage node, a drain terminal coupled to the drain via, and a gate electrode coupled to a signal node. A top portion of at least one of the gate via or the drain via extends between the first and second metal lines.