OTP Memory Cell Dielectric Segmentation for Wider Memory Window
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Solution Overview
Problem
Existing one-time programmable (OTP) memory cells have limited memory window and reliability due to similar breakdown voltages of program and read transistors, leading to difficulty in distinguishing between programmed and unprogrammed states.
Innovation Solution
Increase the number of traps in the program dielectric layer by exposing it to longer etching processes while protecting the read dielectric layer, resulting in a lower breakdown voltage for the program transistor and a larger current difference between programmed and unprogrammed states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the program dielectric layer is exposed to longer etching processes to increase traps, then the memory window and reliability are improved, but the manufacturing complexity and process time increase
Solution Approach 1:
The patent divides the dielectric layer into two distinct segments: a program dielectric layer exposed to longer etching processes to generate traps, and a read dielectric layer protected from excessive etching. This segmentation allows each layer to have optimized properties for its specific function, resolving the contradiction between improving memory window and managing process complexity.
Solution Approach 2:
The patent applies different etching durations to different spatial locations of the dielectric structure. The program dielectric layer receives extended etching exposure to create trap states locally, while the read dielectric layer maintains shorter exposure to preserve its integrity. This local quality differentiation enables improved reliability without uniformly increasing overall process complexity.
2Reliability
If the program transistor breakdown voltage is reduced to increase current difference, then the memory window improves, but the power consumption during programming increases
Solution Approach 1:
The patent modifies the breakdown voltage parameter of the program transistor by controlling the trap density in the program dielectric layer through selective etching. By adjusting this parameter, the patent achieves a lower breakdown voltage that increases the current difference between programmed and unprogrammed states, thereby improving the memory window while managing programming power requirements.
3Object-generated harmful factors
If the read dielectric layer is protected from etching to maintain low leakage, then the leakage current is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the dielectric structure into program and read regions with different etching exposures. By applying masking techniques selectively to the read dielectric layer during etching processes, the patent protects it from trap formation and associated leakage, while allowing the program dielectric layer to be fully exposed for trap generation. This resolves the contradiction between reducing leakage and managing manufacturing complexity.
Solution Approach 2:
The patent introduces masking layers as intermediary elements that control etching exposure. These masking structures act as mediators between the etching process and the read dielectric layer, preventing direct etching damage while allowing the program dielectric layer to be processed. This intermediary approach reduces leakage current in the read path while managing the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the memory window and reliability of OTP memory cells by increasing the second current during read operations, reducing power consumption and leakage, and improving data distinction.
Implementation Method 1
the program dielectric layer has a higher number of traps than the read dielectric layer
Data Source
AI summary
In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.