OTP Memory Cell Layout for Diode Effect and Voltage Stress Relief
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory cells experience diode effects and voltage stress during programming, which affect the read current and reliability of the memory cells.
Innovation Solution
Incorporating an additional dopant region under the gate of the anti-fuse transistor to create an additional current path and using cascaded select transistors to relax voltage stress, along with specific bias voltage application to minimize diode effects and improve read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional OTP memory cells are used, then the device structure is simple, but diode effects and voltage stress occur during programming affecting read current and reliability
Solution Approach 1:
The memory cell is divided into multiple transistor components (first transistor and second transistor) with separate control functions. The first transistor handles programming operations while the second transistor manages reading operations, allowing independent optimization of each component's behavior to reduce overall diode effects and voltage stress.
Solution Approach 2:
An additional dopant region is introduced as an intermediary element between the existing transistor structures. This dopant region creates an additional current path that mediates the electrical flow, reducing the direct impact of diode effects and voltage stress on the read current while maintaining the one-time programmable functionality.
2Object-affected harmful factors
If additional dopant region is added under the gate, then diode effects are reduced, but device complexity increases
Solution Approach 1:
The additional dopant region is placed specifically under the gate of the first transistor, concentrating the structural modification only where it is most effective. This localized approach reduces diode effects in the critical programming region without unnecessarily complicating the entire memory cell structure.
Solution Approach 2:
The dopant region extends in a direction perpendicular to the conventional transistor layers, creating a three-dimensional current path. This dimensional addition allows current to flow through a new pathway that bypasses the harmful diode effect without requiring changes to the planar transistor architecture.
3Stress or pressure
If cascaded select transistors are used, then voltage stress is relaxed, but device complexity increases
Solution Approach 1:
The select transistor function is segmented into two separate transistors connected in cascade. The first select transistor and second select transistor share the voltage stress burden, with each transistor experiencing reduced voltage compared to a single transistor configuration, thereby relaxing the overall voltage stress on the memory cell.
Solution Approach 2:
The cascaded transistor configuration is designed beforehand to cushion against voltage stress. By pre-configuring the transistors in series, the voltage stress that would normally be concentrated on a single transistor is distributed and cushioned across multiple components, preventing excessive voltage stress during programming operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional current path reduces diode effects, while cascaded transistors alleviate voltage stress, enhancing the reliability and performance of OTP memory cells.
Implementation Method 1
An additional fourth dopant region connects to the first dopant region and extends partially under the first gate of the anti-fuse transistor. The additional fourth dopant region forms an additional current path for a read current.
Implementation Method 2
A memory cell is a circuit configured to store a bit of data, typically using one or more transistors.
Data Source
AI summary
Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.