OTP Memory Double Error Detection ECC Decoder
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Solution Overview
Problem
Existing OTP memory devices lack enhanced reliability and usability, particularly in detecting and correcting double bit errors, which affects the overall performance and data integrity in semiconductor memory systems.
Innovation Solution
The proposed OTP memory device incorporates an ECC decoder, a double error fuse address register set, a double error fuse counter, and a control circuit to perform ECC decoding operations, detect double bit errors, and store fuse address information, thereby enhancing reliability and usability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional OTP memory cells are used without ECC decoding, then the device complexity is low, but the reliability is insufficient due to inability to detect and correct double bit errors
Solution Approach 1:
The OTP memory is divided into multiple banks, with each bank containing OTP cell arrays and associated ECC decoding circuits. This segmentation allows independent error handling in each bank while maintaining overall system reliability, resolving the contradiction by distributing complexity across multiple manageable units rather than requiring a monolithic complex structure.
Solution Approach 2:
ECC decoding circuits are introduced as intermediary components between the OTP cell arrays and the data output paths. These intermediary circuits perform error detection and correction functions, enhancing reliability without requiring fundamental changes to the OTP memory structure itself, thus resolving the contradiction between reliability improvement and complexity increase.
2Loss of information
If OTP memory cells are used without double error detection mechanisms, then the manufacturing precision requirements are lower, but the data integrity is compromised due to undetected double bit errors
Solution Approach 1:
The ECC decoding circuits perform preliminary error detection and correction actions before data is read out from the OTP memory. By proactively detecting and correcting errors in the fuse data before it reaches the output stage, the system maintains data integrity without requiring higher manufacturing precision during the fuse programming process itself.
3Ease of operation
If no ECC decoding operation is performed on OTP fuse sets, then the operation speed is faster, but the usability is reduced due to inability to correct single bit errors and detect double bit errors
Solution Approach 1:
The ECC decoding operation is applied selectively to specific portions of the OTP memory data (fuse sets in specific banks) rather than to the entire memory space. This partial application of error correction provides sufficient usability enhancement for critical data while minimizing the speed penalty associated with comprehensive error checking across all data.
Data Source
AI summary
A one-time programmable (OTP) memory device includes an OTP cell array, an error correction code (ECC) decoder, a double error fuse address register set and a double error fuse counter. The OTP cell array includes OTP cell rows, each of the OTP cell rows includes OTP fuse sets and each of the OTP fuse sets includes OTP memory cells. The ECC decoder performs an ECC decoding operation on first OTP fuse sets and activates a double error detection flag in response to a double bit error being detected in a second subset. The double error fuse address register set stores fuse address information of the second subset and the double error detection flag. The double error fuse counter stores a double error counting signal by counting the double error detection flag based on the latch clock signal.