OTP Memory Cell with Embedded Drain Electrode
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices, such as those using EPROM or EEPROM, have large die sizes and complex manufacturing processes, leading to high costs for electronic tags and semiconductor products, while one-time programmable (OTP) memory cells with a PIP structure are costly and require a thick high voltage cell transistor, increasing die area.
Innovation Solution
A nonvolatile semiconductor memory device with a transistor and capacitor structure, where the capacitor includes an impurity-implanted lower electrode, an insulation film, and an upper electrode connected to a data line, allowing for dielectric breakdown to write data, reducing the die area and manufacturing cost by using a thinner capacitor insulation film and a lightly doped drain structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PIP structure OTP memory cell is used to achieve nonvolatile characteristics, then the memory can store data permanently, but the manufacturing process becomes complex and the manufacturing cost increases
Solution Approach 1:
The patent merges the capacitor structure with the transistor drain region by forming the lower electrode of the capacitor within the drain region itself. This integration eliminates the need for separate capacitor formation processes and reduces the number of manufacturing steps while maintaining the nonvolatile memory functionality through dielectric breakdown of the capacitor insulation film
Solution Approach 2:
The drain region of the transistor serves dual purposes: it functions as both the transistor drain and the lower electrode of the capacitor. This multi-functionality reduces the overall device complexity and simplifies the manufacturing process by eliminating redundant structures and processes
2Reliability
If a PIP structure OTP memory cell is used to obtain nonvolatile characteristics, then data can be stored permanently, but the die area increases due to the thick high voltage cell transistor
Solution Approach 1:
The patent merges the capacitor structure with the transistor drain region by forming the lower electrode of the capacitor within the drain region itself. This integration eliminates the need for separate capacitor formation processes and reduces the number of manufacturing steps while maintaining the nonvolatile memory functionality through dielectric breakdown of the capacitor insulation film
Solution Approach 2:
The patent utilizes the vertical dimension within the drain region to form the capacitor lower electrode, effectively using the depth of the drain region rather than expanding the horizontal die area. This allows the capacitor structure to be accommodated within the existing transistor footprint
3Adaptability or versatility
If EPROM or EEPROM is used as memory in electronic tags, then data can be electrically written and rewritten, but the die size becomes large and manufacturing cost increases
Solution Approach 1:
The patent implements a one-time programmable memory cell that uses dielectric breakdown of the capacitor insulation film to store data. This disposable approach (where the insulation film is intentionally destroyed during programming) enables cost-effective manufacturing with simpler processes and smaller die size, while still providing the necessary data storage capability for electronic tags
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a smaller-sized OTP memory cell with reduced manufacturing costs and a simpler process, enabling the production of cost-effective electronic tags and semiconductor products with the ability to write data after initial programming.
Implementation Method 1
The insulation film is configured to break down when a predetermined voltage is applied to the insulation film through a corresponding data line so that a predetermined data is written in the memory device
Implementation Method 2
The capacitor includes an impurity-implanted lower electrode formed in the drain region
Data Source
AI summary
The invention realizes a smaller-sized OTP memory cell and large reduction of its manufacturing process and cost. An embedded layer (BN+) to be a lower electrode of a capacitor is formed in a drain region of a cell transistor of an OTP memory, a capacitor insulation film having a small thickness where dielectric breakdown can occur by a predetermined voltage applied from a data line is formed on this embedded layer, and a conductive layer to be an upper electrode of a capacitor is formed on the capacitor insulation film and on a field oxide film. The embedded layer (BN+) partially overlaps a high concentration drain region (N+).