Dual Vt Program Regions in OTP Memory for Data Retention
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory technologies face challenges in high power consumption and low programming efficiency, particularly with electrical fuse (eFuse) and charge trapping methods, which result in weak data retention and small program windows.
Innovation Solution
The implementation of a semiconductor device with dual Vt program regions in the dielectric region, allowing for asymmetrical programming voltages applied to the source and drain sides, increasing the gate threshold voltage and improving data retention through dual programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If weak program condition is applied to reduce power and energy, then power consumption is reduced, but program window becomes small and data retention performance deteriorates
Solution Approach 1:
The patent divides the programming function into two separate programming methods: a first programming method for normal operation and a second programming method specifically for improving data retention. This segmentation allows the system to use weak program conditions for normal operations while occasionally applying strong program conditions to enhance data retention, thus resolving the contradiction between low power consumption and reliable data retention.
Solution Approach 2:
The patent implements periodic data retention improvement operations where the second programming method is applied at specific intervals (e.g., after a certain number of programming operations or at predetermined time points). This periodic application of strong programming conditions maintains data retention performance without requiring continuous high power consumption, thus resolving the contradiction between power reduction and reliability maintenance.
2Reliability
If eFuse programming is performed by forcing high current density through conductive link, then programming is achieved, but power consumption increases and programming efficiency decreases
Solution Approach 1:
The patent changes the programming parameters by using threshold voltage shift in MOSFET channels instead of rupturing conductive links. This is achieved by applying controlled voltage stresses to create charge traps in the gate dielectric, which shifts the threshold voltage to indicate programming state. This parameter change from high-current link rupture to voltage-controlled threshold shift dramatically reduces power consumption while maintaining reliable programming.
3Reliability
If anti-fuse programming is performed by applying electrical stress to create conductive path, then programming is achieved, but the process requires additional processing complexity increasing costs
Solution Approach 1:
The patent uses standard CMOS MOSFET devices with existing gate dielectric structures to perform OTP memory functionality. The same MOSFET device structure serves both as logic/transistor and as OTP memory cell, eliminating the need for separate anti-fuse structures and their associated complex processing steps. This multi-functionality approach reduces device complexity and manufacturing costs while achieving reliable programming through threshold voltage shift.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the program window and data retention performance by increasing the gate threshold voltage by approximately 300 millivolts and reduces the asymmetry in source and drain current responses, improving programming efficiency.
Implementation Method 1
The use of charge trapping in metal-oxide semiconductor (MOS) transistors, and in particular using channel hot charge (CHC) injection for programming, has been developed.
Implementation Method 2
The use of charge trapping in metal-oxide semiconductor (MOS) transistors, and in particular using channel hot charge (CHC) injection for programming, has been developed.
Implementation Method 3
It may generate charge trap closing in a drain side of gate dielectric when device is programmed due to CHC injection.
Data Source
AI summary
A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.