OTP Memory Testing via Dummy Cell Isolation

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Solution Overview

Problem

One-time programmable (OTP) memory devices are less efficient to test compared to re-programmable memories due to their irreversible programming nature, making it challenging to accurately assess the functionality of peripheral circuits.

Innovation Solution

Incorporating a cell array circuit with an OTP cell array, a dummy cell block, and an isolation circuit that cuts off specific voltages in test modes, allowing for separate testing of row and column decoders and the OTP cell array to determine device defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If OTP memory cells are used for permanent storage, then data retention reliability is improved, but test efficiency deteriorates due to irreversible programming

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidtest efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the memory array into OTP cell blocks and dummy cell blocks, allowing separate testing of peripheral circuits from storage cells. The dummy cell blocks can be re-programmed for testing while OTP cells remain immutable, thus maintaining data retention reliability while improving test efficiency through segmented testing approaches.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If OTP cells cannot be re-programmed, then manufacturing precision is improved for permanent storage, but test accuracy deteriorates due to inability to verify peripheral circuits

Engineering Contradiction:
Improveprogramming precisionVSAvoidtest accuracy
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The patent introduces dummy cell blocks as intermediary elements that can be re-programmed specifically for testing purposes. These dummy cells act as mediators between the test equipment and the peripheral circuits, enabling accurate verification of row decoders, column decoders, and sensing circuits without affecting the immutable OTP storage cells.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If isolation circuit is added to cut off voltages during testing, then test accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvetest accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The isolation circuit incorporates controllable switches that dynamically connect or disconnect voltage supplies to OTP cell blocks based on the operational mode (test mode vs. normal operation mode). This dynamic reconfiguration allows the same hardware to serve dual purposes: enabling isolated testing when needed while maintaining normal memory operation otherwise, thus limiting the increase in device complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10964399B2One-time programmable (OTP) memory devices and methods of testing OTP memory devices
Publication Date: 2021.03.30 SAMSUNG ELECTRONICS CO LTD
  • US10964399B2 patent drawing
  • US10964399B2 patent drawing
  • US10964399B2 patent drawing

AI summary

A one-time programmable (OTP) memory device including: a cell array circuit including an OTP cell array and dummy cell block, the OTP cell array includes OTP memory cells coupled to bit-lines, read word-lines and voltage word-lines and the dummy cell block is coupled to the read word-lines and voltage word-lines; a row decoder coupled to the dummy cell block and the OTP cell array through the read word-lines and voltage word-lines; a column decoder coupled to the OTP cell array through the bit-lines; a write-sensing circuit coupled to the column decoder; and a control circuit to control the cell array circuit, row decoder and write-sensing circuit based on a command and address, the cell array circuit further includes an isolation circuit to cut off first and second voltages which are transferred to the OTP cell array from the row decoder, in response to control codes in a test mode.