OTP Memory Error Detection for Incremental Bit Programming
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Solution Overview
Problem
Existing OTP memories cannot effectively utilize error detection and correction codes (ECC) for incrementally programmed data due to the inability to change programmed bits, limiting robustness in error detection, especially for single-bit errors.
Innovation Solution
Implement programming check bits (PCBs) that can be incrementally generated and updated as bits are programmed over time, combined with redundant bits to provide enhanced error detection, distinguishing between reliability issues and security threats.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC check bits are stored along with each data word in OTP memory, then error detection and correction capability is improved, but the ability to incrementally program data is lost because all bits must be programmed at once
Solution Approach 1:
The patent segments the error detection function into two distinct components: redundant bits that can be incrementally updated, and programming check bits (PCBs) that verify programming integrity. This segmentation allows incremental programming while maintaining robust error detection, resolving the contradiction between reliability and ease of operation.
Solution Approach 2:
The patent introduces dynamic updating of redundant bits alongside static verification through PCBs. The redundant bits can be dynamically updated as data is incrementally programmed, while PCBs provide static verification of programming integrity. This dynamic approach enables incremental programming without sacrificing error detection capability.
2Ease of operation
If redundant bits are used for error detection in OTP memory, then ease of incremental programming is improved, but error detection robustness deteriorates compared to ECC
Solution Approach 1:
The patent merges redundant bits and programming check bits into a unified error detection system. Redundant bits provide incremental update capability while PCBs provide robust verification. Together, they achieve error detection robustness comparable to ECC while maintaining incremental programming capability.
Solution Approach 2:
The patent creates a composite error detection mechanism combining two different approaches: redundant bits for incremental updates and PCBs for robust verification. This composite approach leverages the strengths of both methods to achieve robust error detection without sacrificing incremental programming capability.
3Reliability
If programming check bits are generated based on all OTP value bits, then error detection coverage is improved, but the ability to detect specific error types (single-bit vs. attacks) is reduced
Solution Approach 1:
The patent applies local quality by generating different PCBs based on different subsets of OTP value bits. Some PCBs are generated from specific bit subsets to detect single-bit errors, while others are generated from different subsets to detect attacks. This localized approach enables both comprehensive coverage and precise error type differentiation.
Solution Approach 2:
The patent changes the parameters of PCB generation by using different bit subsets and different generation rules for different PCBs. This allows the system to detect various error types with appropriate precision while maintaining comprehensive coverage through the combination of multiple PCBs.
Data Source
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AI summary
A controller for a one-time-programmable (OTP) memory is configured to, in response to a write request to program a single bit of an OTP value to the OTP memory, program a bit of the OTP value in the OTP memory, generate a set of PCBs corresponding to the OTP value, and program the PCBs into the OTP memory. Each PCB of the set of PCBs is generated as a logic function of a different subset of bits of the OTP value. The logic function only results in each PCB being programmed or remaining programmed in the OTP memory but not cleared. The OTP controller may be configured to, in response to the write request, program both the bit of the OTP value and a redundant bit, in which the set of PCBs includes a first PCB based on the bit and a second PCB based on the redundant bit.