OTP Memory Device Filling Oxide Anti-Fuse Integration
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Solution Overview
Problem
One-time programmable (OTP) memory devices face limitations in data storage capacity due to the irreversible nature of OTP cells, which restricts their integration density and ability to store increased data without increasing device size.
Innovation Solution
The OTP memory device incorporates a filling oxide layer on a silicon-on-insulator (SOI) substrate, functioning as an anti-fuse, allowing for enhanced data storage by utilizing the breakdown characteristics of the oxide layer to implement multiple states, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional OTP cells are used with irreversible programming, then device structure remains simple, but data storage capacity is limited
Solution Approach 1:
The patent divides the OTP cell into multiple functional components: access transistor, filling oxide layer (first anti-fuse), and gate insulation layer (second anti-fuse). This segmentation allows independent programming of each component, enabling multiple storage states without requiring a completely complex redesign of the entire cell structure.
Solution Approach 2:
The patent introduces a temporal dimension to the programming process by programming the filling oxide layer first, then programming the gate insulation layer afterward. This sequential programming approach enables the cell to store multiple states (0, 1, 2, 3) by combining the states of the two programmable components, effectively increasing storage capacity without proportionally increasing structural complexity.
2Quantity of substance
If multiple states are implemented in OTP cell, then data storage capacity increases, but programming control complexity increases
Solution Approach 1:
The programming control is segmented into two independent phases: first programming the filling oxide layer (first anti-fuse), then programming the gate insulation layer (second anti-fuse). Each phase can be controlled independently, simplifying the overall control logic compared to a single complex programming mechanism.
Solution Approach 2:
The filling oxide layer is programmed first as a preliminary action, establishing a foundational state before the gate insulation layer is programmed. This preliminary programming enables subsequent programming operations to build upon the established state, making the multi-state programming process more manageable and controllable.
3Quantity of substance
If filling oxide layer is added as anti-fuse, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The filling oxide layer is merged with the existing SOI substrate structure and integrated into the standard CMOS manufacturing process. By combining the anti-fuse function with the substrate fabrication rather than adding a separate discrete component, the patent increases integration density while minimizing the impact on manufacturing process complexity.
Solution Approach 2:
The filling oxide layer serves multiple functions: it acts as the first anti-fuse for programming, provides structural support as part of the SOI substrate, and integrates with the existing CMOS process. This multi-functionality allows the same structural element to contribute to both storage capacity and manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the storage of more data compared to conventional OTP memory devices, enhancing the integration degree and allowing for the implementation of multiple states within a single OTP memory cell, thereby improving data storage capacity.
Implementation Method 1
The filling oxide layer on the silicon-on-insulator (SOI) substrate, functioning as an anti-fuse, allowing for enhanced data storage by utilizing the breakdown characteristics of the oxide layer
Implementation Method 2
The access transistor may include a gate structure on a substrate, and first and second impurity regions at respective portions of the substrate adjacent to the gate structure
Data Source
AI summary
A one-time programmable (OTP) memory device includes an access transistor, a word line, a voltage line, a well, a first filling oxide layer, a first semiconductor layer, and a bit line. The access transistor includes a gate structure on a substrate, and first and second impurity regions at portions of the substrate adjacent to the gate structure. The word line is electrically connected to the gate structure. The voltage line is electrically connected to the first impurity region. The well is formed at an upper portion of the substrate, and is doped with impurities having a first conductivity type. The first filling oxide layer is formed on the well. The first semiconductor layer is formed on the first filling oxide layer, and is doped with impurities having the first conductivity type and electrically connected to the second impurity region. The bit line is electrically connected to the well.