OTP Memory Fuse Bit Reading via Sequential Latch Control
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Solution Overview
Problem
One-time programmable (OTP) memory devices are limited in their ability to read multiple fuse bits due to the restriction of the number of input-output lines, which hinders their performance and reliability.
Innovation Solution
The implementation of a latch controller and latch circuit that generates sequential latch address signals to connect bitline groups to input-output lines, allowing for the storage and reading of a greater number of fuse bits than the input-output lines, enhancing the OTP memory device's performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of input-output lines is increased to read more fuse bits, then the reading capability is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The bitline array is divided into multiple bitline groups (first bitline group, second bitline group, etc.), each group being selectively connected to input-output lines through the column selection circuit. This segmentation allows multiple fuse bits to be read sequentially through the same physical input-output lines, effectively increasing the readable fuse bit capacity without proportionally increasing the number of input-output lines.
Solution Approach 2:
The column selection circuit dynamically reconfigures the connection between bitline groups and input-output lines based on the latch address signal. By sequentially connecting different bitline groups to the same input-output lines under different latch address signals, the system enables reading of multiple fuse bits (N*M fuse bits) through a limited number of input-output lines (M lines), resolving the contradiction between reading capability and device complexity.
2Loss of information
If sequential reading of multiple fuse bits is implemented, then the information capacity is improved, but the reading time increases
Solution Approach 1:
The latch controller generates periodic latch address signals that sequentially select different bitline groups for reading. By organizing the reading process into periodic cycles where each cycle reads a portion of fuse bits through the same input-output lines, the system achieves efficient sequential reading of N*M fuse bits, minimizing the time penalty while maximizing information capacity.
Solution Approach 2:
The latch circuit is pre-configured to store the expected N*M fuse bits, and the column selection circuit is pre-arranged to connect bitline groups to input-output lines based on predetermined latch address signals. This preliminary configuration enables the sequential reading process to proceed efficiently without dynamic reconfiguration delays, reducing the overall reading time while maintaining high information capacity.
Data Source
AI summary
A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.