OTP Memory Security Against Glitch Attacks
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Solution Overview
Problem
Integrated circuits (ICs) with secure memory are vulnerable to glitch attacks, which can spoof hardware embedded security sequences, potentially allowing unauthorized access to secure data, and existing solutions fail to effectively detect such faults in real-time.
Innovation Solution
The method involves sampling values from multiple OTP memory arrays and comparing them to an unprogrammed array value to determine if a fault has occurred, with the IC operating in secure or non-secure modes based on these comparisons, thereby controlling access to memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware embedded security sequences are implemented using OTP memory to protect secure memory, then data protection is improved, but the system becomes vulnerable to glitch attacks that can spoof the security sequences
Solution Approach 1:
The patent divides the security sequence verification into multiple independent OTP memory arrays (first OTP memory array, second OTP memory array, third OTP memory array). Each array stores a portion of the security sequence, allowing the system to detect glitches by comparing results across multiple arrays rather than relying on a single sequence. This segmentation makes it more difficult for attackers to spoof all sequences simultaneously.
Solution Approach 2:
The patent implements a feedback mechanism where the sampled values from multiple OTP memory arrays are compared against each other and against expected unprogrammed array values. The comparison results feed back to determine whether a glitch attack has occurred, triggering appropriate response actions such as blocking access to secure memory. This closed-loop verification system continuously monitors for tampering attempts.
2Measurement precision
If multiple OTP memory arrays are sampled and compared to detect faults, then detection precision is improved, but device complexity increases
Solution Approach 1:
The patent designs the OTP memory arrays to serve multiple functions: storing security sequences for authentication, providing test patterns for fault detection, and enabling mode determination (secure vs. non-secure operation). The same hardware infrastructure (OTP arrays, sampling circuitry, comparison logic) is used for both normal operation and fault detection, reducing the need for separate dedicated components.
Solution Approach 2:
The patent utilizes changes in the electrical or physical state of OTP memory devices during sampling and comparison operations to detect faults. By monitoring parameter changes (such as voltage thresholds, current characteristics, or timing parameters) during the sampling process, the system can identify deviations that indicate tampering or hardware faults without requiring complex analysis of the entire memory content.
3Reliability
If real-time fault detection is implemented to prevent unauthorized access, then security response time is improved, but processing time increases due to multiple comparisons
Solution Approach 1:
The patent performs preliminary sampling and comparison of OTP memory array values during the system initialization or boot-up process, before normal operation begins. By completing the fault detection verification early in the timeline, the system establishes the security state (secure mode or non-secure mode) in advance, allowing rapid response without delaying subsequent operations. The unprogrammed array values are pre-determined and stored for quick comparison.
Data Source
AI summary
One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination.