OTP Memory Array Layout With Mixed Cell Characteristics for IR Drop
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Solution Overview
Problem
Existing OTP memory devices face performance issues due to high voltage IR drop on word and bit lines, which is exacerbated by the increasing density of memory cells, affecting the efficiency and performance of integrated circuits.
Innovation Solution
The memory device is configured with multiple portions of memory cells having different electrical and physical characteristics, where transistors in one portion are formed in the FEOL network and those in another portion are formed in the BEOL network, with varying threshold voltages to mitigate IR drop effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased to improve integration density, then more components can be integrated into a given area, but voltage IR drop on word and bit lines increases, degrading performance
Solution Approach 1:
The patent applies local quality by creating different portions of memory cells with different electrical characteristics. Specifically, first portions have transistors with first threshold voltages while second portions have transistors with second threshold voltages. This allows different regions of the memory array to have optimized characteristics for their specific locations, compensating for IR drop effects in distant cells while maintaining high integration density across the entire array.
2Reliability
If transistors are formed in FEOL network to achieve certain electrical characteristics, then specific performance is achieved, but device complexity increases when multiple networks are used
Solution Approach 1:
The patent segments the memory array into different portions (first portions and second portions) that are formed using different transistor networks (FEOL and BEOL). This segmentation allows each portion to be optimized for its specific function and location, with FEOL transistors providing certain electrical characteristics in some regions and BEOL transistors providing different characteristics in other regions, thereby managing complexity through structured division rather than uniform design.
Solution Approach 2:
The patent utilizes parameter changes by varying the threshold voltage parameter of transistors across different portions of the memory array. By changing the threshold voltage parameter between first portions and second portions, the invention optimizes electrical characteristics for different locations in the array, addressing IR drop effects while maintaining a manageable manufacturing process through systematic parameter variation rather than fundamental process complexity.
Data Source
AI summary
A memory device includes a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion, wherein the first and second portions are disposed next to each other along a first lateral direction; a first driver circuit disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion and the first driver circuit along the first lateral direction; and a second driver circuit disposed next to both of the first and second portions along a second lateral direction perpendicular to the first lateral direction. The OTP memory cells of the first portion are associated with a first electrical/physical characteristic and the OTP memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.