OTP Memory Cell P-Drift Region Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing one-time programmable (OTP) memory devices face challenges in maintaining precision power management post-package due to stress and charge-induced variations, requiring improved post-package trimming techniques that are costly and complex, especially with sub-micron CMOS technologies, where the efficiency of electron injection into the floating gate is limited by the low concentration N-dopant lightly doped drain (LDD) region.
Innovation Solution
Implementing a single polysilicon OTP with a P-drift region that increases substrate dopant concentration near the drain, enhancing the electrical field for hot electron creation, and using a PMOS coupling capacitor in a common N-well, where the P-drift region is simultaneously formed as the source and drain for the PMOS device, eliminating additional implanting steps and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If a deep heavily doped N region is used in the drain region to increase the electrical field, then the electrical field at the drain region increases, but the LDD region is wiped out and manufacturing complexity increases
Solution Approach 1:
The patent changes the doping concentration parameter by introducing a P-type drift region with higher dopant concentration than the LDD region. This creates a graded doping profile that maintains the electrical field enhancement needed for hot electron injection while avoiding the complete wipeout of the LDD region, thus reducing manufacturing complexity
Solution Approach 2:
The patent uses a composite doping structure combining both N-type (LDD) and P-type (drift region) dopants in the drain region. This composite structure allows the P-type drift region to enhance the electrical field while the N-type LDD region remains partially intact, achieving both high electrical field and reduced manufacturing complexity
2Productivity
If Fowler-Nordheim tunneling is used to collect electrons in the floating gate, then electron collection efficiency improves, but the trimming voltage required increases
Solution Approach 1:
The patent modifies the electrical field distribution parameter in the drain region by introducing the P-type drift region. This creates a more concentrated high-field region that enhances hot electron generation efficiency, allowing effective electron collection in the floating gate at lower trimming voltages
Solution Approach 2:
The patent replaces the reliance on high-voltage Fowler-Nordheim tunneling with a hot electron injection mechanism enhanced by the P-type drift region. This substitution allows electron collection through thermal excitation in the high-field region rather than requiring high-voltage tunneling
3Measurement precision
If the coupling capacitor is made six to ten times larger than the NMOS gate capacitance to achieve proper voltage division, then the coupling ratio is optimized, but the device area increases
Solution Approach 1:
The patent changes the threshold voltage parameter of the NMOS transistor by introducing the P-type drift region. This threshold voltage modulation allows for better voltage control during programming, effectively optimizing the coupling ratio without requiring a large coupling capacitor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves higher programming efficiency and reliability with reduced manufacturing complexity and cost, maintaining a higher threshold voltage for the first MOS transistor while ensuring regular operation of the second MOS transistor, thus addressing the limitations of prior art OTP devices.
Implementation Method 1
enhancing the electrical field for hot electron creation
Implementation Method 2
The electrons are collected using different techniques such as Fowler-Nordheim tunneling
Implementation Method 3
an NMOSFET with a floating gate that is coupled to the control gate through a coupling capacitor
Data Source
AI summary
This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed with a single polysilicon stripe. The method further comprises a step of implanting a drift region in a substrate region below a drain and source of the first and second MOS transistors counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region.