OTP Memory Cells Preconfigured to Eliminate High-Voltage Programming

Solution Overview

Problem

Existing one-time-programmable (OTP) memory devices face issues such as potential damage to other device features during programming due to high voltage/current signals and excessive power consumption.

Innovation Solution

The OTP memory device includes memory cells that are preconfigured to default logic states without programming, with efuse cells having a fuse resistor and WL transistor in series, and anti-fuse cells having a programming transistor and reading resistor in series, allowing for default 0 and default 1 states that cannot be altered.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If high voltage/current signals are used for programming OTP memory devices, then the memory can be programmed to desired logic states, but other device features may be damaged and power consumption increases

Engineering Contradiction:

Improveprogramming capabilityVSAvoiddamage to device features

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by preconfiguring memory cells to default logic states during fabrication without requiring subsequent programming. Efuse cells are preconfigured to default 0 state with connected fuse resistors, and anti-fuse cells are preconfigured to default 1 state with broken fuse resistors. This eliminates the need for high voltage/current programming signals that cause damage and power consumption.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If high voltage/current signals are used for programming OTP memory devices, then the memory can be programmed to desired logic states, but power consumption increases

Engineering Contradiction:

Improveprogramming capabilityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by preconfiguring memory cells to default logic states during fabrication without requiring subsequent programming. Efuse cells are preconfigured to default 0 state with connected fuse resistors, and anti-fuse cells are preconfigured to default 1 state with broken fuse resistors. This eliminates the need for high voltage/current programming signals that cause damage and power consumption.

Inventive Principle:

Principle #10Preliminary action

3Use of energy by moving object

If memory cells are preconfigured to default logic states, then programming processes are eliminated and power consumption is reduced, but the logic states cannot be altered

Engineering Contradiction:

Improvepower consumptionVSAvoidprogrammability

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary action by preconfiguring memory cells to default logic states during fabrication without requiring subsequent programming. Efuse cells are preconfigured to default 0 state with connected fuse resistors, and anti-fuse cells are preconfigured to default 1 state with broken fuse resistors. This eliminates the need for high voltage/current programming signals that cause damage and power consumption.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies inversion by reversing the conventional OTP approach: instead of starting with unprogrammed cells that require high-voltage programming to set logic states, the patent starts with cells preconfigured to default states and uses low-voltage signals only to read or invert the state if needed. This inverts the programming paradigm from active programming to passive preconfiguration.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20250351340A1One-time-programmable memory devices

Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device is disclosed. The memory device includes a memory array comprising a plurality of memory cells. At least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. At least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.