OTP Memory Cell Layout for Unclonable PUF Authentication
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Solution Overview
Problem
Existing memory devices lack a reliable method to generate unique, unclonable signatures for authentication and secret key storage without requiring expensive hardware, as they rely on digital memory which can be replicated despite manufacturing variability.
Innovation Solution
The implementation of a memory device with efuse cells featuring two fuse resistors and multiple transistors, where the programming voltage randomly blows one fuse resistor before the other, generating a unique PUF signature based on which resistor is blown, thereby leveraging manufacturing variability for authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If digital memory is used for authentication, then device complexity is reduced, but security is compromised due to replicability
Solution Approach 1:
The patent converts manufacturing variability, which is typically a harmful factor causing defects, into a beneficial feature for generating unique authentication signatures. Each device's inherent process variations create distinct PUF signatures that cannot be replicated, thus improving security while maintaining simple memory structure.
Solution Approach 2:
Instead of storing authentication data in replicable digital memory, the patent uses physical unclonable functions based on manufacturing variations. The PUF signature is derived from the unique physical characteristics of each device, making it impossible to copy or replicate the authentication credentials.
2Reliability
If expensive hardware is used for secure authentication, then security is improved, but cost increases
Solution Approach 1:
The patent replaces expensive secure hardware with a cost-effective PUF-based authentication mechanism that leverages existing manufacturing processes. The authentication security is derived from inherent physical variations rather than expensive cryptographic hardware, significantly reducing manufacturing costs while maintaining security.
Solution Approach 2:
The manufacturing process itself generates the authentication credentials through inherent process variations. No additional expensive hardware or separate authentication component is needed - the device automatically possesses unique PUF signatures as a byproduct of its fabrication, making authentication self-service and cost-effective.
3Device complexity
If OTP memory cells are formed in FEOL, then integration is simplified, but area consumption increases
Solution Approach 1:
The patent moves the fuse resistors and control gate transistors from the planar FEOL layer to the vertical BEOL metallization layers. This dimensional transition allows the authentication structure to utilize the third dimension (vertical stacking), reducing the footprint in the planar area while maintaining integration with the logic circuitry.
Solution Approach 2:
The patent embeds the PUF authentication structure within the existing BEOL interconnect layers. The fuse resistors are formed in metal layers that are already part of the logic device structure, nesting the authentication functionality within the existing device architecture without requiring separate dedicated space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for secure authentication and secret key storage without expensive hardware, as each memory device generates a unique signature due to inherent manufacturing variations, enhancing security and reducing costs.
Implementation Method 1
the programming voltage randomly blows one fuse resistor before the other, generating a unique PUF signature
Data Source
AI summary
A memory device includes an array having a plurality of one-time-programmable (OTP) memory cells formed over a side of a substrate, a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of control gate (CG) lines. Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and the second fuse resistors are connected to a corresponding one of the BLs, while the first and the second transistors are respectively gated by a first one and a second one of the CG lines. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are respectively formed in a first one, a second one, a third one, and a fourth one of a plurality of metallization layers disposed on the side of the substrate.


