OTP Memory Cell Readout Using a Reference Anti-Fuse Path
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory elements in integrated circuits (ICs) face challenges in efficiently programming and reading anti-fuse bits due to variations in dielectric breakdown voltages, leading to inconsistent data retention and reliability issues.
Innovation Solution
A novel OTP memory cell design incorporating a substrate with source and drain regions, a gate oxide, and a gate structure that allows for precise control of programming by applying specific voltage levels to break down the gate oxide, creating a reliable current path for data storage, and a read operation that distinguishes programmed and un-programmed states based on bit line voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a programming electric field is applied across the dielectric material layer to break it down, then the resistance of the dielectric material layer decreases and data can be stored, but variations in dielectric breakdown voltages cause inconsistent data retention and reliability issues
Solution Approach 1:
The patent introduces a reference cell as an intermediary element that has the same dielectric material and structure as the test cell but is pre-programmed to a known state. This reference cell serves as a mediator to compensate for variations in dielectric breakdown voltage by providing a baseline for comparison during read operations, thereby improving data retention consistency without requiring precise control of breakdown voltage variations.
Solution Approach 2:
The patent implements a feedback mechanism by comparing the current through the test cell with the current through the reference cell during read operations. This feedback comparison allows the system to detect and compensate for variations in dielectric breakdown voltage, ensuring consistent data retention by adjusting read conditions based on the relative current measurements.
2Measurement precision
If read voltage is applied across the dielectric material layer to determine anti-fuse bit status, then current can be read to determine programmed state, but variations in dielectric properties lead to inconsistent read results
Solution Approach 1:
The reference cell acts as an intermediary that provides a stable reference point for measurement. By comparing the test cell's current against the reference cell's current during read operations, the system achieves more accurate and consistent measurement of programmed state, eliminating the impact of dielectric property variations on read accuracy.
Solution Approach 2:
The patent changes the measurement approach by transitioning from absolute current measurement to relative current measurement through comparison with a reference cell. This parameter change from absolute to relative measurement compensates for dielectric variations and improves both read accuracy and data retention consistency.
3Duration of action of stationary object
If the gate oxide is broken down to create a current path for data storage, then the memory cell can retain data without power supply, but the breakdown process must be precisely controlled to ensure one-time programmability
Solution Approach 1:
The reference cell serves as an intermediary that enables precise control of the programming process. By using the reference cell to establish a baseline for current measurement, the system can accurately determine when the gate oxide has broken down and data has been successfully programmed, ensuring consistent and reliable one-time programmability without requiring extremely precise voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design ensures reliable, one-time programmable data storage with consistent read operations, maintaining data integrity even without power supply, by utilizing transistors as switching elements and precise voltage control to differentiate programmed and un-programmed states.
Implementation Method 1
a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer
Implementation Method 2
utilizing transistors as switching elements and precise voltage control to differentiate programmed and un-programmed states
Implementation Method 3
provide non-volatile memory ('NVM') in which data are not lost when the IC is powered off
Data Source
AI summary
An OTP memory device includes a substrate, a first transistor, a second transistor, a first word line, second word line, and a bit line. The first transistor includes a first gate structure, and first and second source/drain regions on opposite sides of the first gate structure. The second transistor is operable in an inversion mode, and the second transistor includes a second gate structure having more work function metal layers than the first gate structure of the first transistor, and second and third source/drain regions on opposite sides of the second gate structure. The first word line is over and electrically connected to the first gate structure of the first transistor. The second word line is over and electrically connected to the second gate structure of the second transistor. The bit line is over and electrically connected to the first source/drain region of the first transistor.