One-Time Programmable Memory Device with Shared Write Control Circuit
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Solution Overview
Problem
Conventional one-time programmable (OTP) memory devices using electrical-fuse elements increase in size due to the inclusion of sense circuits and latch circuits for each storage cell, making it difficult to reduce their size while maintaining stable operation and efficient writing capabilities.
Innovation Solution
A nonvolatile semiconductor memory device with a cell array of storage cells connected in series to a selection switch, a row selection control circuit, and a write control circuit that controls voltage bit by bit on data lines, allowing for selective programming of storage cells by breaking insulating films, thereby reducing the overall size without compromising writing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense circuits and latch circuits are provided for each e-fuse element, then stable operation is achieved, but the memory size greatly increases
Solution Approach 1:
The patent merges the sense circuit and latch circuit functions into shared circuit blocks that are common to multiple storage cells. Instead of having dedicated circuits for each e-fuse element, the invention uses shared readout circuits and control logic that can service multiple cells, thereby reducing the overall memory area while maintaining stable operation.
Solution Approach 2:
The patent implements universal circuit blocks that can perform multiple functions across different storage cells. The same readout circuit can read from different cells by selecting them through control signals, and the latch circuit can be reused for different cells sequentially, making the circuits multi-functional and reducing the total number of circuits required.
2Productivity
If a write control circuit is provided for each e-fuse element, then writing operations can be performed exactly, but the memory size cannot be decreased
Solution Approach 1:
The patent combines multiple write control circuit functions into a single shared write control circuit that can service multiple e-fuse elements. This shared circuit uses control signals to selectively activate different storage cells for writing, thereby maintaining writing operation precision while reducing the number of individual write control circuits needed.
Solution Approach 2:
The patent introduces dynamic control mechanisms that allow the shared write control circuit to adaptively select which storage cell should be written to at any given time. Through dynamic control signals, the circuit can switch between different cells based on the write data being input, maintaining precise writing control without requiring dedicated static control circuits for each cell.
3Duration of action of stationary object
If the memory uses e-fuse elements, then it can store information permanently, but the writing process requires high voltage that may damage the element
Solution Approach 1:
The patent incorporates protection circuits that are activated before the high voltage is applied to the e-fuse element. These protection circuits include voltage regulation mechanisms and current limiting circuits that prevent excessive voltage or current from damaging the element during the writing process, while still allowing the necessary high voltage to break the insulating film for permanent storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact OTP memory device that can perform writing operations bit by bit, maintaining operational speed and efficiency while reducing the physical size, as the write control circuit discharges data lines connected to cells written with '1' one by one, sharing sense amplifiers and circuit blocks across data lines.
Implementation Method 1
programmed with information by breaking an insulating film of the storage element
Data Source
AI summary
A nonvolatile semiconductor memory device having a storage element which is programmed with information by breaking an insulating film of the storage element, includes a cell array including a plurality of storage cells arranged in matrix, each of the storage cells having the storage element and a selection switch connected in series to the storage element, and a row selection control circuit which activates a row selection line connected to a given number of storage cells. The device further includes a write control circuit which controls a voltage of each of data lines bit by bit in accordance with write data, the data lines being connected to a given number of storage cells connected to the row selection line activated by the row selection control circuit.