OTP Memory Cell Using Silicide Migration for Reliable Programming
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Solution Overview
Problem
Conventional programmable read-only memories (PROMs) face reliability issues due to the breakdown of gate oxides or metal/polymeric materials, and high-current densities require large control transistor sizes, increasing the size and cost of bit cells.
Innovation Solution
A one-time programmable memory cell is implemented using a single transistor with source-contact silicide migration, where a programming current increases the source resistance by causing silicide to migrate into the source region, achieved through CMOS processing without additional layers or masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate oxide breakdown or metal strip breakdown is used for programming, then the memory cell can be programmed, but the reliability of the PROM is reduced
Solution Approach 1:
The patent converts the harmful effect of high current density into a beneficial effect by utilizing it to induce silicide migration. Instead of causing destructive breakdown as in conventional methods, the high current density is controlled to migrate silicide from the source contact into the source region, increasing source resistance in a non-destructive manner that serves the programming function while maintaining reliability.
2Reliability
If high-current density is used to program the fuse, then the fuse can be programmed, but the control transistor size must be large
Solution Approach 1:
The patent employs self-service by allowing the high current density itself to induce the desired silicide migration effect without requiring external control mechanisms. The current automatically causes silicide to migrate into the source region, increasing source resistance and achieving programming in a self-regulating manner that eliminates the need for large control transistors.
3Reliability
If large control transistor size is used, then the fuse can be programmed with high current density, but the bit cell size and cost increase
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of the transistor, specifically increasing the source resistance through silicide migration. This parameter change enables the transistor to function as a programmable element without requiring changes to the physical size or structural complexity of the bit cell, thereby maintaining compact dimensions while achieving reliable programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell reliability and reduces the footprint while maintaining cost-effectiveness by utilizing a single transistor with increased source resistance for programming, avoiding damage to other cells in an array.
Implementation Method 1
conducting a programming current through the drain region and the source region may cause a source-contact silicide to migrate into the source region
Implementation Method 2
increasing a source resistance of the transistor based on migration of the source-contact silicide into the source region
Data Source
AI summary
A memory cell is disclosed. The memory cell comprises a transistor. The transistor includes a gate, a drain region coupled to a drain terminal by one or more drain contacts, and a source region coupled to a source terminal by a source contact. A cumulative drain-contact area of the one or more drain contacts of the transistor is greater than a source-contact area of the transistor. Further a source-contact silicide is located between the source contact and the source region, and the source-contact silicide is configured to migrate into the source region in response to a programming current conducted through the drain region and the source region.