OTP Memory Subarray Segmentation for Voltage Stress Reduction
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Solution Overview
Problem
The existing OTP memory systems face challenges in reducing gate-oxide voltage stress during programming, which can lead to time-dependent dielectric breakdown and require substantial IC area due to the use of higher-rated devices to withstand programming voltages.
Innovation Solution
The OTP memory system partitions memory cells into subarrays, using core devices rated for lower voltages and applying the programming voltage to fewer FETs, reducing the duration and extent of exposure to minimize stress and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher-rated devices with thicker gate oxide are used to withstand programming voltage, then device reliability under programming voltage is improved, but IC area occupied by the memory increases
Solution Approach 1:
The memory array is divided into multiple subarrays, where only one subarray is programmed at a time. This segmentation allows the use of lower-rated core devices in each subarray while limiting the number of devices exposed to high programming voltage simultaneously, thus reducing total IC area while maintaining reliability.
2Productivity
If programming voltage is applied to more FETs simultaneously, then programming speed is improved, but stress on FETs and risk of time-dependent dielectric breakdown increase
Solution Approach 1:
The memory is organized into subarrays that can be programmed sequentially. This allows parallel programming capability within each subarray while distributing the stress burden across multiple subarrays over time, achieving high overall programming speed without subjecting all FETs to high voltage simultaneously.
Solution Approach 2:
The programming operation is performed in periodic cycles, with each cycle targeting a specific subarray. This periodic approach allows the system to maintain high programming throughput by switching between subarrays while giving each subarray sufficient recovery time, reducing cumulative stress on individual FETs.
3Area of stationary object
If lower-rated core devices are used to reduce IC area, then IC area is reduced, but devices become vulnerable to programming voltage stress
Solution Approach 1:
By dividing the memory into subarrays and limiting programming operations to one subarray at a time, the patent enables the use of smaller, lower-rated core devices in each subarray. The segmentation ensures that no single device is exposed to excessive cumulative stress, allowing area reduction while maintaining reliability.
Solution Approach 2:
The patent implements a programming scheme that distributes voltage stress across multiple subarrays sequentially, providing a form of beforehand cushioning. By carefully controlling which subarray is programmed at each time step and limiting the duration of high-voltage exposure for each device, the system protects vulnerable core devices from damage while achieving compact implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the stress on FETs and IC area by limiting the number of FETs subjected to the programming voltage, preventing damage and allowing for a more compact memory implementation with core devices.
Implementation Method 1
This produces a current through the corresponding fuse element and FET sufficient to blow the fuse element (e.g., produce an open in the fuse metallization due to electromigration)
Data Source
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AI summary
A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to receiving a second asserted signal via a global word line and a third asserted signal.