OTP Memory Testing Circuit Checkerboard Pattern
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for testing One-Time Programmable (OTP) memory cells are inadequate, as they cannot effectively verify the virgin and non-virgin states of OTP memory cells and associated peripheral circuits, leading to potential defects that go undetected until after packaging.
Innovation Solution
The implementation of additional OTP cells and control signals to generate checkerboard-like patterns, enable/disable wordlines and Y-Pass Gates arbitrarily, and use multiple reference resistance levels to test resistance distributions, allowing for thorough characterization of OTP memory states and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used for OTP memory cells, then the testing process is simple, but defects in virgin and non-virgin states and peripheral circuits cannot be detected
Solution Approach 1:
The testing method segments the OTP memory array into different testable regions by selectively enabling even or odd wordlines and bitlines, allowing independent testing of virgin and non-virgin states without requiring additional physical test structures
Solution Approach 2:
The invention performs preliminary programming of specific OTP cells to create known virgin and non-virgin states before conducting the actual test, enabling detection of defects by comparing expected versus actual readback values
Solution Approach 3:
The testing methodology changes operational parameters by selectively activating different wordlines and bitlines to create checkerboard patterns, allowing the same memory array to be tested in multiple configurations without hardware modifications
2Reliability
If additional OTP cells are added for testing, then comprehensive testing of virgin and non-virgin states is enabled, but the memory array size increases
Solution Approach 1:
The existing OTP memory array structure is made multi-functional by enabling it to serve both as storage memory and as a self-testing structure, eliminating the need for separate dedicated test cells
Solution Approach 2:
The test functionality is merged with the normal memory array operation by using the same wordlines, bitlines, and sense amplifiers for both regular memory access and defect detection testing
3Measurement precision
If multiple reference resistance levels are used to test resistance distributions, then read performance characterization is improved, but the testing complexity increases
Solution Approach 1:
The testing process uses periodic action by sequentially applying different reference resistance levels and systematically enabling/disabling wordlines and bitlines in a structured sequence, allowing comprehensive resistance distribution characterization through repeated measurement cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables comprehensive testing of OTP memory cells in both virgin and non-virgin states, detecting defects and ensuring the OTP memory is fully functional, while also characterizing resistance distributions for improved read performance.
Implementation Method 1
The OTP element can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between.
Implementation Method 2
The programming means can apply a high voltage to an OTP element such as in anti-fuse. Alternatively, the programming means can apply a high current to flow through an OTP element such as in fuse.
Data Source
AI summary
Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.