OTP Memory Transistor Overlap Optimization
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Solution Overview
Problem
One-time programmable (OTP) memory devices face limitations in program efficiency due to the fixed nature of their memory cells, which restricts their ability to rewrite data, and existing technologies do not effectively enhance this efficiency.
Innovation Solution
The OTP memory device is designed with a series connection of selection and storage transistors, featuring a floating gate structure and a unique arrangement of gate electrodes and impurity ion implantation techniques to optimize channel lengths and overlap areas, allowing for improved program efficiency and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the overlapping region between source region and floating gate structure is reduced, then program efficiency is enhanced, but the channel length of storage transistor is increased
Solution Approach 1:
The patent applies local quality by creating different overlapping region lengths at different locations within the storage transistor. Specifically, the overlapping region between the source region and floating gate structure is made shorter than the channel length, while maintaining adequate overlap between the common junction region and floating gate. This localized differentiation allows the channel to be longer for better efficiency while the source-floating gate overlap is minimized for reduced interference, resolving the contradiction between program efficiency and channel length.
2Speed
If the channel length of storage transistor is increased, then program speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the geometric parameters of the transistor structure, specifically setting the overlapping region length between source region and floating gate to be less than the channel length. This parameter modification allows the channel to extend further without proportionally increasing the source-floating gate overlap, thereby improving program speed while controlling power consumption through optimized structural dimensions rather than uniform scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances program speed and efficiency while minimizing power consumption by increasing the channel length of storage transistors and reducing the overlap area between the source region and floating gate, enabling faster programming and data storage.
Implementation Method 1
Logical information may be stored in the OTP memory cell by injecting charges into the floating gate. Since the floating gate is electrically isolated, the charges stored in the floating gate may still remain even after a power supply voltage applied to the OTP memory cell is interrupted.
Implementation Method 2
a third type of impurity ions are implanted into the substrate between the floating gate structure and the selection gate structure adjacent thereto, and between the selection gate structures adjacent to each other
Data Source
AI summary
A one-time programmable (OTP) memory device includes a plurality of unit cells which are respectively located at cross points of word lines and bit lines. Each unit cell includes a selection transistor and a storage transistor coupled in series. The selection transistor includes a drain region and a common junction region separated by a first channel region and includes a selection gate structure disposed on the first channel region. The storage transistor includes a source region and the common junction region separated by a second channel region and includes a floating gate structure disposed on the second channel region. A length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction.