OTP Memory Voltage Isolation for High-Voltage Damage Prevention
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Solution Overview
Problem
High voltage during programming in prior art OTP memory cells can cause damage and reduce reliability, affecting the reading of cells through Sense Amplifiers.
Innovation Solution
Incorporating a Voltage Isolator in Series comprising three N-type or P-type MOS transistors, with a voltage-limit device that limits the gate voltage of the second MOS transistor, reducing voltage stress on the anti-fuse element and sensor MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied during programming in prior art OTP memory cells, then programming can be achieved, but the high voltage causes damage and leakage to the sensor MOS transistor, reducing reliability
Solution Approach 1:
A voltage isolator circuit is introduced as an intermediary component between the programming voltage line and the sensor MOS transistor. This isolator limits the voltage that reaches the sensor transistor during programming operations, preventing high voltage damage while allowing normal read operations. The voltage isolator acts as a protective mediator that blocks harmful high voltage from reaching sensitive components.
Solution Approach 2:
The memory cell structure is segmented into distinct functional regions with independent voltage control. The voltage isolator creates a separation between the high-voltage programming path and the low-voltage sensing path, allowing each component to operate within its safe voltage range. This segmentation enables the sensor MOS transistor to be protected from programming voltage while still functioning during read operations.
2Productivity
If high voltage is used for programming, then programming function is achieved, but voltage stress on the anti-fuse element and sensor MOS transistor increases, causing degradation
Solution Approach 1:
The voltage isolator serves as a mediator that enables programming functionality while reducing voltage stress on critical components. During programming, the isolator allows sufficient voltage to pass through to program the anti-fuse element, but limits the voltage reaching the sensor MOS transistor, thereby maintaining productivity while improving stability.
Solution Approach 2:
The voltage isolator dynamically changes the voltage parameter based on operational mode. During programming operations, it allows higher voltage transmission to program the anti-fuse, while during read operations or when protecting the sensor transistor, it limits the voltage to safe levels. This parameter control resolves the contradiction between achieving programming function and reducing voltage stress.
3Reliability
If high voltage programming is used, then programming is achieved, but the damaged sensor MOS transistor affects reading through Sense Amplifier
Solution Approach 1:
The voltage isolator is configured to protect the sensor MOS transistor before damage can occur. By limiting voltage stress during programming operations in advance, the isolator prevents the transistor from degrading into a leakage state. This preliminary protective action ensures that the sensor transistor remains reliable for subsequent read operations through the Sense Amplifier.
Solution Approach 2:
The voltage isolator acts as a protective intermediary that prevents harmful voltage from reaching the sensor MOS transistor during programming. This mediation ensures that the transistor does not suffer damage that would generate leakage currents, thereby maintaining reading reliability through the Sense Amplifier without requiring additional corrective measures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of OTP memory cells by preventing damage and leakage from high voltage, allowing for reduced programming and reading voltages, thereby improving overall memory array performance and reducing the size of row decoders.
Implementation Method 1
there is a voltage-limit device (3), which has one control end and two connection ends. The control end of the voltage-limit device is connected to the control line WB. One of the connection end of device (3) is connected to the first line WP across through the anti-fuse element. The other connection end of device (3) is connected to the gate of the second MOS transistor.
Data Source
AI summary
A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.