OTP Memory Cell Voltage Limiting for Reliability
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Solution Overview
Problem
Existing non-volatile memory cells for one-time programmable (OTP) applications in high frequency and ultra high frequency RFID systems face issues with high voltage damage and leakage in MOS transistors, leading to reliability concerns and inefficiencies in programming and reading operations.
Innovation Solution
Incorporation of a voltage-limit device, specifically a third MOS transistor, which limits the gate voltage of the second MOS transistor during programming, preventing damage and ensuring low reading voltage operations by connecting it between the anti-fuse element and the gate of the second MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high voltage programming is applied to OTP memory cells, then programming capability is achieved, but MOS transistor damage and leakage occur
Solution Approach 1:
A voltage-limit device (third MOS transistor) is introduced as an intermediary component between the programming voltage source and the second MOS transistor. This device mediates the voltage transmission, allowing high voltage programming to proceed while blocking excessive voltage from reaching the second MOS transistor, thus preventing damage during programming operations
Solution Approach 2:
The voltage-limit device dynamically changes the voltage parameter transmitted to the second MOS transistor based on operational conditions. During programming, it limits the gate voltage to a safe level (e.g., 1.8V or lower) even when high programming voltage is applied, thereby changing the voltage parameter to protect the transistor while still enabling programming functionality
2Reliability
If voltage-limit device is added to protect MOS transistor, then reliability is improved, but device complexity increases
Solution Approach 1:
The voltage-limit device (third MOS transistor) serves multiple functions simultaneously: it limits voltage during programming to protect the second MOS transistor, acts as a switching element for programming operations, and integrates seamlessly with the existing memory cell structure. This multi-functionality reduces the need for additional dedicated protection components, thereby minimizing the increase in device complexity while achieving reliable protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces voltage stress on the gate oxide layer of the second MOS transistor, enhancing reliability and preventing damage, thereby improving the performance and longevity of OTP memory cells.
Implementation Method 1
there is a voltage-limit device (3), which has one control end and two connection ends. The control end of the voltage-limit device is connected to the control line WB. One of the connection end of device (3) is connected to the anti-fuse element and the end of the first MOS transistor. The other connection end of device (3) is connected to the gate of the second MOS transistor.
Data Source
AI summary
The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals.