OTP Memory Cell Array Voltage Programming Architecture
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Solution Overview
Problem
Existing OTP memory devices face inaccuracies in programming operations due to mismatched voltages when multiple power lines are required for driving OTP cell arrays, leading to inefficient programming processes.
Innovation Solution
The OTP memory device employs an external supply voltage-driven architecture without a source line, utilizing a PMOS and NMOS configuration with a NAND gate to perform programming operations independently of the bit line, and includes a power selection circuit to manage voltage levels and routing, allowing simultaneous selection and programming of OTP memory cells by data input circuits and column decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power lines are used to drive OTP cell arrays with different voltages, then programming operations can be performed, but voltage mismatch occurs leading to inaccurate programming
Solution Approach 1:
The patent removes the source line from the OTP memory cell structure, eliminating the need for multiple power lines with different voltages. The programming operation is achieved by applying voltage only to the bit line and word line, while the source line is completely extracted from the cell configuration.
Solution Approach 2:
The bit line is designed to serve multiple functions: it acts as both the data input line and the power supply line for programming operations. By making the bit line universal, the patent eliminates the need for separate source lines and reduces the number of power lines required.
2Ease of manufacture
If source lines are included in OTP memory cells, then programming operations can be driven with controlled voltages, but circuit layout size increases and costs rise
Solution Approach 1:
The source line is completely removed from the OTP memory cell structure. This extraction eliminates the additional circuitry and layout space required for source lines, directly reducing the overall circuit layout size while maintaining programming capability through the bit line.
Solution Approach 2:
The functionality of the source line is merged into the bit line. The bit line now performs both its traditional data transmission function and the power supply function previously handled by the source line, consolidating the circuit structure and reducing layout area.
3Ease of operation
If different voltages are applied to source lines for programmed vs unprogrammed cells, then programming operation can be controlled, but voltage mismatch occurs reducing programming accuracy
Solution Approach 1:
The patent changes the voltage application parameters by eliminating the need for different voltage levels on source lines. Instead, a single voltage level is applied to the bit line for all programming operations, regardless of the cell state, thereby avoiding voltage mismatch and improving programming accuracy.
Solution Approach 2:
Instead of controlling programming by applying different voltages to source lines based on cell state, the patent inverts the approach by applying voltage uniformly to the bit line and using the absence or presence of conductive paths within the cell to determine programming state, thereby eliminating voltage mismatch issues.
Data Source
AI summary
An OTP memory device includes an OTP memory cell array including OTP memory cells driven by an external supply voltage, the OTP memory cells comprising bit lines arrayed in rows and columns; data input circuits respectively connected to the rows of the OTP memory cells and configured to select a row of the OTP memory cells to which the supply voltage is to be applied; a column decoder connected to each column of the OTP memory cells and configured to select columns of the OTP memory cells to which the supply voltage is to be applied; and a detection amplifier connected to the bit line and configured to perform a read operation of the OTP memory cells.