OTP MRAM Tunnel Barrier Thickness via Surface Topology
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Solution Overview
Problem
Magnetic random access memory (MRAM) bits designed for multi-time-programmable (MTP) applications have high breakdown voltage, making it difficult to integrate one-time-programmable (OTP) bits with reduced breakdown voltage without manufacturing control issues, as existing methods require small device sizes that are challenging to produce reliably.
Innovation Solution
Forming OTP MRAM elements on substrates with surface topology to thin the tunnel barrier, allowing for reduced breakdown voltage by creating non-coplanar surfaces where the tunnel barrier is thinner, enabling co-processing with MTP MRAM bits using a single process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OTP MRAM elements are made smaller to reduce breakdown voltage, then breakdown voltage is reduced, but manufacturing precision deteriorates due to control issues
Solution Approach 1:
The patent applies local quality by creating surface topology variations (non-coplanar regions) at specific locations where OTP MRAM elements are formed. This causes the tunnel barrier to have different thicknesses in different regions, with thinner regions providing lower breakdown voltage for OTP elements, while maintaining uniform thickness for MTP elements in planar regions. This resolves the contradiction by achieving breakdown voltage reduction through local structural modification rather than global size reduction.
Solution Approach 2:
The patent transitions from controlling breakdown voltage through two-dimensional device size reduction to three-dimensional surface topology control. By introducing vertical dimension variations (non-coplanar surfaces) into the substrate, the invention achieves breakdown voltage differentiation without compromising planar manufacturing precision. The surface topology creates localized thickness variations in the tunnel barrier while maintaining overall device dimensions suitable for standard manufacturing processes.
2Productivity
If MTP and OTP MRAM bits are co-processed using the same process, then manufacturing efficiency is improved, but device performance deteriorates due to inability to differentiate breakdown characteristics
Solution Approach 1:
The patent enables co-processing of MTP and OTP MRAM bits by creating local quality differences in the substrate surface topology. OTP elements are formed in non-coplanar regions with thinner tunnel barriers for lower breakdown voltage, while MTP elements are formed in planar regions with uniform thickness for higher breakdown voltage. This allows both device types to be manufactured using the same process sequence while maintaining distinct electrical characteristics through localized structural variations.
Solution Approach 2:
The patent segments the substrate surface into distinct topological regions (coplanar and non-coplanar areas) that serve different functional purposes. This segmentation allows simultaneous formation of MTP and OTP elements with different breakdown characteristics using a single manufacturing process, resolving the contradiction between manufacturing efficiency and device performance differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the breakdown voltage of OTP MRAM bits while allowing for simultaneous integration with MTP bits on the same chip, improving manufacturing efficiency and reducing manufacturing control issues.
Implementation Method 1
by forming the OTP MRAM element over the surface topology the tunnel barrier has both a first thickness T1 and second thickness T2, wherein T1 is greater than T2
Data Source
AI summary
Techniques for forming OTP memory elements with reduced breakdown voltage are provided. In one aspect, a method of forming an OTP MRAM element includes the steps of: creating a substrate having surface topology; and forming the OTP MRAM element on the substrate over the surface topology, wherein the OTP MRAM element comprises a first magnetic metal layer and a second metal magnetic layer separated by a tunnel barrier, and wherein by forming the OTP MRAM element over the surface topology the tunnel barrier has both a first thickness T1 and second thickness T2, wherein T1 is greater than T2. A method of forming a device having both MTP MRAM and OTP MRAM elements is provided, as is an MRAM device.