OTP Memory Nonce Generation via Random Bit Walk
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Solution Overview
Problem
Integrated circuits with one-time programmable non-volatile memory (OTP NVM) face challenges in preventing replay attacks and efficiently generating secure nonces, as they lack rewritable storage for updating trust anchors and cryptographic keys, leading to limited OTP memory usage and predictability issues.
Innovation Solution
A method is introduced to generate a sequence of nonces by randomly selecting and programming un-programmed bits in the OTP memory, ensuring high entropy and unpredictability, thereby maintaining security while minimizing OTP memory consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional methods store nonces in OTP memory, then security is maintained, but the number of usable nonces is limited due to fixed storage capacity
Solution Approach 1:
The patent transforms the static OTP memory into a dynamic resource by generating nonces through a walk through the memory space. Instead of storing complete nonces statically, the system dynamically generates new nonces by traversing from a starting point through unprogrammed bits, allowing the same physical memory to produce multiple different nonces depending on the walk path and random seed used.
Solution Approach 2:
The patent adds a temporal/dimensional aspect to memory usage by introducing the concept of a 'walk' through memory space. Rather than using memory positions directly as nonces, the system creates nonces by tracing paths through memory over time, effectively adding a time dimension to the static memory structure and enabling multiple nonces from the same physical storage.
2Ease of manufacture
If nonces are generated using fixed patterns, then generation is simple, but predictability compromises security
Solution Approach 1:
The patent performs preliminary actions by establishing a random seed and defining a starting point in the OTP memory before generating any nonces. This preliminary setup ensures that subsequent nonce generation follows a predetermined but unpredictable path based on the random seed, making the nonces不可预测 while maintaining a simple generation process.
Solution Approach 2:
The patent introduces a random seed as an intermediary element between the fixed memory structure and the generated nonces. This random seed acts as a mediator that transforms the deterministic memory layout into unpredictable nonce values, maintaining simplicity in generation while ensuring security through the randomness introduced by the seed.
3Productivity
If OTP memory is fully utilized for nonce storage, then maximum nonces are available, but memory consumption increases
Solution Approach 1:
The patent segments the OTP memory into multiple walk paths rather than using it as a single monolithic storage space. By dividing the memory traversal into sequential steps along different paths from the starting point, the system can generate multiple nonces by exploring different segments of memory, effectively multiplying the usable nonce capacity without proportionally increasing the physical memory required.
Solution Approach 2:
The patent implements a nested structure where nonces are generated by nesting walk paths within the OTP memory space. Each nonce corresponds to a nested path through the memory, and multiple nonces can be generated by nesting different paths at different levels, allowing efficient use of the limited OTP memory capacity to produce a large number of unique nonces.
Data Source
AI summary
A method for generating a secure nonce using a one-time programmable (OTP) memory within an integrated circuit to provide persistence, the method including randomly selecting k currently-unprogrammed bits in the OTP memory, creating a data set using data derived from current contents of the OTP memory altered by changing the states of the k currently-unprogrammed bits of the OTP memory, and employing as the secure nonce the data set or data derived from the data set. The selected k bits are programmed in the OTP memory.