OTP Memory Sensing via Complementary Bitline Voltage Differential
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory technologies, such as anti-fuse OTP memories, face limitations in speed and density due to reliance on special processing steps and high voltage exposure, which affects manufacturability and reliability, and are slow compared to DRAM, impacting system performance in applications like set-top boxes and cell phones.
Innovation Solution
A memory array architecture with complementary bitlines, a precharge circuit, and a bitline sense amplifier that allows for high-speed sensing by precharging bitlines to a voltage level and driving wordlines to switch programmed OTP memory cells, enabling fast voltage differential sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional current sensing schemes are used in anti-fuse OTP memories, then the memory can be manufactured with standard processes, but the sensing speed is slow compared to DRAM
Solution Approach 1:
The patent replaces the traditional current-based sensing mechanism with a voltage-based sensing mechanism. By precharging bitlines to a reference voltage and detecting voltage differentials caused by charge transfer from programmed anti-fuse cells, the system achieves DRAM-compatible sensing speeds without requiring mechanical or temporal sequential operations.
Solution Approach 2:
The invention changes the sensing parameter from current measurement to voltage measurement. The sense amplifier detects voltage differentials on precharged bitlines rather than measuring current flow, fundamentally altering the physical quantity being measured to achieve faster sensing speeds comparable to DRAM technology.
2Reliability
If high voltage exposure is used for programming anti-fuse cells, then the memory can be programmed reliably, but the manufacturability and reliability are affected due to special processing steps
Solution Approach 1:
The patent applies preliminary thick oxide formation to specific regions before standard CMOS processing. By pre-defining breakdown-resistant zones with thicker gate oxide in the channel area while maintaining thin oxide at the drain edge, the structure is prepared in advance to withstand programming voltages without requiring special high-voltage processing steps during manufacturing.
Solution Approach 2:
The invention implements non-uniform gate oxide thickness across the channel region. The gate oxide is made thicker in the channel area to prevent breakdown during programming, while the drain edge region maintains thin oxide to enable reliable anti-fuse formation. This local differentiation of oxide quality allows standard CMOS processing to be used while achieving programming reliability.
3Reliability
If thicker gate oxide is used in the channel area, then the access transistor can withstand programming voltage, but the breakdown voltage of the anti-fuse must be lowered
Solution Approach 1:
The patent segments the gate oxide structure into distinct regions with different thicknesses. The channel area receives thick oxide to prevent transistor breakdown, while the drain edge region receives thin oxide to enable anti-fuse breakdown at controlled voltages. This spatial segmentation of oxide thickness resolves the contradiction between transistor reliability and anti-fuse programmability.
Solution Approach 2:
The invention creates local variations in gate oxide quality and thickness. By making the oxide thicker in the channel region and thinner at the drain edge, the structure achieves both high breakdown resistance in the transistor channel and low breakdown voltage for anti-fuse formation, eliminating the need for precise uniform thickness control across the entire gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed and reliability of anti-fuse OTP memory sensing, overcoming the limitations of existing technologies by enabling high-speed data state detection in non-volatile memories, improving overall system performance without requiring special processing steps.
Implementation Method 1
a precharge circuit for precharging the pair of complementary bitlines to a voltage level
Implementation Method 2
driving one bitline of the pair of complementary bitlines to a second voltage level through a programmable conductive link of a corresponding OTP memory cell
Implementation Method 3
a bitline sense amplifier for sensing a voltage differential on the pair of complementary bitlines
Data Source
Figure 1~3
Figure 4~5
Figure 6a~7b
AI summary
A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.