OTP Memory Silicide Extraction for Reading Current
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Solution Overview
Problem
Current one-time programmable (OTP) memory devices face challenges with weak reading current and longer stress time under program mode, limiting their performance and efficiency.
Innovation Solution
The fabrication method involves forming shallow trench isolations (STIs) and specific gate structures on a substrate, with a silicide layer adjacent to the gate structures but not between them, and using a diffusion break structure to prevent silicide formation between divided source lines, enhancing the OTP memory device's architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicide layer is formed between divided source lines in conventional OTP memory devices, then the fabrication process is simplified, but the silicide layer causes interference that weakens reading current and increases programming stress time
Solution Approach 1:
The patent extracts and removes the silicide layer from the region between divided source lines. By selectively eliminating the silicide layer in this specific area while maintaining it elsewhere, the invention resolves the contradiction by removing the harmful interference that weakens reading current, while preserving the fabrication simplicity of the salicide process for other regions.
Solution Approach 2:
The patent applies local quality by creating a non-uniform silicide layer distribution. The silicide layer is present adjacent to gate structures for proper electrical contact but deliberately absent between divided source lines. This localized modification allows the device to maintain ease of manufacture through standard salicide processes while improving reading current strength by eliminating interference in the critical region between source lines.
2Ease of manufacture
If a silicide layer is formed between divided source lines, then the fabrication process is simplified, but the stress time during programming increases
Solution Approach 1:
The patent extracts and removes the silicide layer from the region between divided source lines. By selectively eliminating the silicide layer in this specific area while maintaining it elsewhere, the invention resolves the contradiction by removing the harmful interference that increases programming stress time, while preserving the fabrication simplicity of the salicide process for other regions.
Solution Approach 2:
The patent applies local quality by creating a non-uniform silicide layer distribution. The silicide layer is present adjacent to gate structures for proper electrical contact but deliberately absent between divided source lines. This localized modification allows the device to maintain ease of manufacture through standard salicide processes while reducing programming stress time by eliminating interference in the critical region between source lines.
3Ease of manufacture
If gate structures are formed with standard processes, then the fabrication is straightforward, but the architecture does not optimize reading current performance
Solution Approach 1:
The patent modifies the standard gate structure formation process by controlling the silicide layer deposition and patterning steps. The gate structures maintain their standard configuration adjacent to diffusion regions, but the silicide layer is selectively removed between divided source lines. This local modification to the gate structure architecture improves reading current performance by eliminating silicide interference while maintaining fabrication straightforwardness through conventional process steps.
Data Source
AI summary
A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.