OTPROM Array Multi-Bit Storage via Gate Oxide Thickness and TDDB Stress
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Solution Overview
Problem
Conventional OTPROM arrays require significant chip area due to the repetition of devices storing only one bit of memory, limiting their storage capacity.
Innovation Solution
A method is developed to program n-type field effect transistors (NFETs) in an OTPROM array to store four data states by varying the gate oxide layer thickness and applying time-dependent dielectric breakdown (TDDB) stress, allowing for twice the bit storage without increasing the array's size, using a multi-bit sense amplifier to detect and read the states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional OTPROM devices store only one bit per device, then the programming and reading processes are simple, but the chip area increases significantly to achieve higher storage capacity
Solution Approach 1:
The patent applies parameter changes by utilizing two different parameters for storage: gate oxide thickness (two levels) and TDDB stress application (two levels), creating four distinct current levels. This allows each device to store 2 bits instead of 1 bit, doubling the storage capacity without increasing chip area or device complexity
Solution Approach 2:
The patent introduces an additional dimension to the storage mechanism by combining physical gate oxide thickness variation with electrical TDDB stress breakdown. This dual-dimensional approach creates four distinguishable states (00, 01, 10, 11) from two binary parameters, enabling 2-bit storage per device while maintaining the same physical device structure
2Quantity of substance
If OTPROM devices are repeated to increase storage capacity, then the storage capacity increases, but the chip area increases proportionally
Solution Approach 1:
The patent makes each NFET device multi-functional by enabling it to store 2 bits through four distinguishable current levels. This universal approach allows the same device structure to perform multiple storage functions, effectively doubling capacity without adding more devices or increasing chip area
Solution Approach 2:
The patent merges two storage mechanisms (gate oxide thickness control and TDDB stress breakdown) into a single device operation. By combining these two binary control methods, the system achieves 2-bit storage capacity in each device, doubling the effective storage density without requiring additional chip area
3Area of stationary object
If multi-bit storage is implemented per device, then the storage capacity doubles without increasing chip area, but the programming method becomes more complex
Solution Approach 1:
The patent segments the 2-bit binary code into two separate parts: the first part controls gate oxide thickness and the second part controls TDDB stress application. This segmentation allows independent control of two binary parameters, simplifying the programming process while achieving 2-bit storage capacity without increasing chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the OTPROM array to store twice the number of bits as conventional arrays without expanding the chip area, enhancing storage capacity in semiconductor devices.
Implementation Method 1
selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code
Data Source
AI summary
A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.