Out-Plane Inductors for High Density IC Packages
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Solution Overview
Problem
On-plane integrated inductors in ROM Integrated circuit device packages face challenges in achieving high inductance values due to dielectric and metal material constraints, and as devices shrink, eddy currents cause signal integrity issues, complicating board space requirements.
Innovation Solution
The implementation of out-plane inductors, which are non-planar inductors with at least one feature extending perpendicularly from a dielectric surface, allowing for higher inductance values and better space utilization while minimizing the overall system height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If on-plane integrated inductors are used in ROM integrated circuit device packages, then the inductors can be integrated into the dielectric surface, but achieving sufficiently high inductance values becomes difficult due to dielectric and metal material process constraints
Solution Approach 1:
The patent transitions from planar (2D) inductor designs to three-dimensional (3D) inductor structures that extend vertically from the dielectric surface. This dimensional change allows the inductor to utilize the z-direction for additional turns and larger effective area, achieving higher inductance values without being constrained by the limited planar space and material process constraints of conventional on-plane designs.
2Productivity
If devices and packages continue to shrink in size, then device density increases, but eddy currents within the device package create signal integrity problems
Solution Approach 1:
The patent extracts the inductor structure from the traditional planar configuration and repositions it as a vertical out-plane structure. This extraction from the conventional layout reduces the inductor's footprint area, allowing closer spacing of device components and improving device density while the vertical orientation minimizes eddy current paths that would otherwise degrade signal integrity in shrunk packages.
3Manufacturing precision
If inductors are removed from device packages and placed nearby on the associated printed circuit board, then inductor constraints are relieved, but board space requirements increase and complexity increases
Solution Approach 1:
The patent merges the inductor function with the device package structure by integrating the out-plane inductor directly into the package substrate or interposer. This combination allows the inductor to be manufactured as part of the package assembly process rather than as a separate component, achieving high-performance inductance characteristics while utilizing otherwise unused vertical space and avoiding additional board space requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Out-plane inductors enable higher inductance values, reduce eddy current issues, and optimize space usage, addressing the constraints of on-plane inductors and signal integrity problems in shrinking device packages.
Implementation Method 1
a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface in an arc-like shape
Implementation Method 2
as devices and packages continue to shrink in size, effects of eddy currents within a device package could create signal integrity problems
Data Source
AI summary
An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.


