Outer Code Layout for Solid State Memory Error Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Error correction in solid state memory devices, particularly non-volatile memory devices, becomes increasingly complex as technology advances to smaller dimensions and multi-bit storage, requiring enhanced error correction methods to protect against block, die, and chip failures.
Innovation Solution
The implementation of concatenated coding using both inner and outer codes, where outer code words span multiple blocks, die, and chips, and are interleaved with inner code words, allowing for error correction and protection across various memory entities, utilizing Reed-Solomon codes and modulator/demodulator circuitry to encode, store, and decode data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used in solid state memory devices, then the basic data protection is provided, but the complexity of error correction increases and reliability is insufficient for block, die, and chip failures
Solution Approach 1:
The patent divides the error correction system into two distinct segments: inner code words that protect individual pages within blocks, and outer code words that protect across multiple blocks, die, or chips. This segmentation allows each code type to specialize in protecting against specific failure modes, improving overall reliability while managing complexity through modular design
Solution Approach 2:
The patent implements a nested coding structure where outer code words encompass and protect multiple inner code words. The outer code words span across multiple blocks, die, or chips and provide hierarchical protection that contains and organizes the inner code protection layers, creating a nested defense system that improves reliability without linearly increasing complexity
2Reliability
If outer code words span multiple blocks, die, and chips to provide comprehensive protection, then reliability improves, but the device structure and code organization become more complex
Solution Approach 1:
The patent segments the memory device into hierarchical units (blocks containing pages, die containing blocks, chips containing die) and assigns specific code words to protect each level. Inner code words protect pages within blocks, while outer code words protect across blocks, die, and chips. This segmentation creates a clear organizational structure that manages complexity through defined boundaries and responsibilities at each level
Solution Approach 2:
The patent extends the protection scope from a single-dimension (within-block) to multiple dimensions by having outer code words span across blocks, die, and chips simultaneously. This multi-dimensional approach allows comprehensive protection while organizing complexity across different spatial and hierarchical dimensions rather than concentrating it in a single structure
3Reliability
If inner code words and outer code words are interleaved and stored in memory cells, then error correction capability is enhanced, but the manufacturing and decoding process becomes more complex
Solution Approach 1:
The patent segments the decoding process into two distinct stages: first decoding inner code words to correct errors within individual pages, then decoding outer code words to correct errors across multiple pages, blocks, die, or chips. This segmentation of the decoding process makes the complex manufacturing and decoding task manageable by breaking it into sequential, specialized steps rather than requiring a single complex decoder
4Reliability
If multiple code words are stored in each page with overlapping symbols, then data protection is improved, but the storage efficiency and access speed may be reduced
Solution Approach 1:
The patent segments data protection by assigning different code words to different granularities: inner code words protect individual pages for fast access, while outer code words provide broader protection across multiple pages. This segmentation allows the system to retrieve data at appropriate speeds based on the protection level needed, maintaining productivity while improving reliability
Solution Approach 2:
The patent applies preliminary error correction by decoding inner code words first to correct errors within pages before attempting to retrieve data. This preliminary action removes many errors early in the process, allowing faster and more reliable data retrieval without needing to process all outer code words, thus maintaining productivity while improving protection
Data Source
AI summary
Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.