Output Amplifier Bias Layout for Synchronized Slew Rate Control
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Solution Overview
Problem
Existing display driver technologies face challenges in controlling slew rates of output amplifiers while minimizing chip occupancy area and power consumption, leading to display blurring due to timing differences in bias voltage changes across the chip.
Innovation Solution
An output amplifier circuit is designed with a main bias circuit generating bias control currents that are converted to bias voltages by sub-bias circuits, allowing for controlled slew rates across amplifiers, reducing circuit area and power consumption by centralizing bias control signal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of adjustment steps of bias voltage is increased to improve slew rate control precision, then the precision of slew rate control is improved, but the number of elements in each sub-bias circuit increases and power consumption increases
Solution Approach 1:
The patent divides the amplifiers into multiple groups and assigns a dedicated sub-bias circuit to each group. Each sub-bias circuit generates bias voltages with multiple adjustment steps to control the slew rates of amplifiers in its group. This segmentation allows precise slew rate control for each group while distributing the circuit complexity across multiple independent sub-circuits rather than requiring one large complex circuit for all amplifiers.
Solution Approach 2:
The sub-bias circuits generate multiple bias voltages with different voltage values corresponding to different adjustment steps. By changing the bias voltage parameters, the slew rates of the amplifiers can be precisely controlled. The patent employs current mirrors to generate these multiple bias voltages from a reference current, allowing precise parameter control without proportionally increasing power consumption across the entire system.
2Reliability
If multiple sub-bias circuits are disposed for each amplifier group to reduce timing difference of bias voltage change, then the timing synchronization is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the amplifiers into multiple groups and places a sub-bias circuit near each group. This spatial segmentation reduces the timing difference of bias voltage changes between chip center and chip end, as each sub-bias circuit is physically closer to the amplifiers it controls, reducing signal propagation delays.
Solution Approach 2:
The patent introduces a main bias circuit as an intermediary that generates a reference current which is then distributed to multiple sub-bias circuits through current mirrors. This intermediary structure allows centralized control while enabling distributed bias voltage generation, reducing the need for complex individual control circuits at each amplifier while maintaining timing synchronization.
3Device complexity
If a single bias circuit is disposed in chip center to simplify circuit structure, then the device complexity is reduced, but the timing difference of bias voltage change between chip center and chip end increases causing display blur
Solution Approach 1:
Instead of using a single centralized bias circuit, the patent segments the bias circuit functionality into one main bias circuit and multiple sub-bias circuits. The main bias circuit remains in the chip center to simplify the overall structure, while sub-bias circuits are distributed near amplifier groups to reduce timing differences in bias voltage delivery across the chip.
Solution Approach 2:
The patent merges the bias voltage generation functionality into a hierarchical structure where the main bias circuit generates a reference current that is then mirrored and distributed to multiple sub-bias circuits. This combining approach allows the system to achieve both centralized control (simplifying structure) and distributed delivery (reducing timing differences).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively shortens rising and falling edge times of output voltages while reducing power consumption and chip area, enhancing display performance by synchronizing bias voltage changes across the chip.
Implementation Method 1
the 1st to K-th sub-bias circuits generate the plurality of bias voltages based on voltages acquired by performing current-to-voltage conversion on the bias control currents received by the sub-bias circuits
Data Source
AI summary
An output amplifier circuit includes: 1st to K-th sub-bias circuits configured to be disposed in correspondence with 1st to K-th amplifier groups acquired by dividing 1st to n-th amplifiers for every predetermined number of amplifiers, generate a plurality of bias voltages for setting current values of operation currents of the amplifiers, and supply the bias voltages to amplifiers belonging to corresponding amplifier groups; and a main bias circuit configured to supply K currents having current values corresponding to voltage values designated by a control signal designating the voltage values of bias voltages to the 1st to K-th sub-bias circuits as 1st to K-th bias control currents, in which the 1st to K-th sub-bias circuits generate the plurality of bias voltages based on voltages acquired by performing current-to-voltage conversion on the bias control currents received by the sub-bias circuits among the 1st to K-th bias control currents.