Output Amplifier Clamp Circuit for High-Slew Display Waveforms
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-definition display apparatuses, the rapid driving time per pixel leads to increased slew rates, causing ringing issues due to instantaneous overshoot and undershoot in drive waveforms, particularly in organic electroluminescence displays, where a solution is needed to suppress these effects while maintaining high slew rates.
Innovation Solution
The implementation of an output amplifier with a drive voltage generating unit, an output unit comprising complementary transistors, and clamp voltage generating circuits that apply positive and negative clamp voltages to the transistors, reducing the room for overshooting and undershooting, thereby suppressing ringing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the slew rate of the output amplifier is increased to meet shorter pixel driving times in high-definition displays, then the response speed improves, but ringing occurs due to instantaneous overshoot and undershoot in the drive waveform
Solution Approach 1:
The clamp voltage generating circuits generate clamp voltages in advance based on the input voltage before the output amplifier switches. By applying these pre-calculated clamp voltages to the power supply terminals during switching transitions, the patent prevents overshoot and undershoot before they can occur, allowing high slew rate operation without ringing in organic EL displays
Solution Approach 2:
The clamp voltage generating circuits act as intermediary components between the input voltage source and the output amplifier power supply terminals. These circuits process the input voltage to generate appropriate clamp voltages that mediate the power supply to the output transistors, preventing direct overshoot/undershoot effects while maintaining the high slew rate capability
Data Source
AI summary
An output amplifier which includes a drive voltage generating unit that generates a positive drive voltage and a negative drive voltage corresponding to a difference between an input voltage and an output voltage, an output unit including a first transistor and a second transistor forming a complementary output between a positive power supply terminal and a negative power supply terminal, the first transistor flowing out the current from the positive power supply terminal to the output terminal corresponding to the positive drive voltage, and the second transistor flowing the current from the output terminal into the negative power supply terminal corresponding to the negative drive voltage, and clamp voltage generating circuits that apply a positive clamp voltage corresponding to the input voltage to the positive power supply terminal and apply a negative clamp voltage corresponding to the input voltage to the negative power supply terminal.