Output Buffer Impedance Calibration Using Binary Search Codes
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Solution Overview
Problem
High data transfer rates between semiconductor devices require precise impedance adjustment of output buffers, which is challenging due to variations in manufacturing conditions, temperature, and power supply voltage, and is further complicated by the need for clock signal synchronization, leading to reduced determination time and accuracy in comparator voltage detection.
Innovation Solution
A semiconductor device with a data output terminal and two buffers controlled by adjustment codes, using a binary search method to generate and update adjustment codes for impedance adjustment, allowing for efficient impedance calibration within a prescribed time while maintaining sufficient determination time for the comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is increased to improve data transfer rate, then the productivity is improved, but the determination time for voltage comparison decreases and measurement precision deteriorates
Solution Approach 1:
The patent segments the impedance adjustment process into multiple bits (first bit through fourth bit), where each bit is adjusted independently in order of significance. This segmentation allows the system to complete adjustments in fewer clock cycles by focusing on the most significant bits first, thereby reducing the total determination time while maintaining measurement precision.
Solution Approach 2:
The patent applies preliminary action by first determining the most significant bit (first bit) of the impedance adjustment code before proceeding to less significant bits. This approach allows the system to establish the primary impedance characteristic early in the calibration process, reducing the overall calibration time while ensuring accurate voltage comparison for the most critical parameters.
2Manufacturing precision
If the impedance adjustment is performed stepwise in synchronization with clock signal to improve manufacturing precision, then the measurement precision is improved, but the time required for calibration increases
Solution Approach 1:
The patent divides the impedance adjustment into segmented bits (first bit through fourth bit) and adjusts them in hierarchical order from most significant to least significant. This segmentation enables the calibration to be completed in a fixed number of clock cycles (four cycles for four bits) rather than requiring exhaustive stepwise adjustment, thereby reducing calibration time while maintaining manufacturing precision.
Solution Approach 2:
The patent implements a dynamic adjustment strategy where the adjustment code is updated based on comparison results in real-time during calibration. The system dynamically determines the optimal impedance setting by sequentially adjusting bits based on voltage comparison outcomes, allowing precise impedance control to be achieved faster than static stepwise methods.
3Measurement precision
If the determination time is extended to improve voltage comparison accuracy, then the measurement precision is improved, but the calibration period becomes excessively long
Solution Approach 1:
The patent segments the voltage comparison process into multiple independent comparison stages, each corresponding to a specific bit of the adjustment code. By comparing voltages and determining bit values sequentially in four distinct stages rather than performing one exhaustive comparison, the system achieves accurate voltage detection while limiting the total calibration period to a fixed number of clock cycles.
Solution Approach 2:
The patent applies partial action by determining only the necessary number of bits (four bits) required to achieve the desired impedance precision, rather than continuing adjustments until absolute maximum precision is reached. This approach provides sufficient measurement precision for practical purposes while preventing the calibration period from becoming excessively long.
Data Source
AI summary
To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.