Output Buffer Impedance Matching with Two-Stage Code Latching
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Solution Overview
Problem
Conventional impedance matching systems for output buffer circuits in integrated circuit chips face issues such as noise creation, power inefficiency, and electromigration due to frequent recalculations of p-code and n-code values, which can lead to significant switching noise and lengthy update processes.
Innovation Solution
The implementation of an output buffer using a two-stage latch configuration to store updated p-code and n-code values, operating with a divided clock signal of lower frequency than the output clock signal, and adjusting these values by certain percentages using a multiplication function for fine-tuning, thereby shortening the switching sequence and reducing noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If impedance matching logic frequently recalculates p-code and n-code values to maintain consistent impedance matching, then impedance matching accuracy is improved, but switching noise and power consumption increase
Solution Approach 1:
The patent implements periodic impedance matching updates triggered by freeze signals, rather than continuous recalibration. The impedance matching logic updates p-code and n-code values only when a freeze signal indicates stable operating conditions, reducing unnecessary switching noise while maintaining adequate impedance matching accuracy for varying temperature and voltage conditions
Solution Approach 2:
The patent performs preliminary impedance matching calculations during idle periods or before critical operations. By pre-calculating and storing optimal p-code and n-code values in advance, the system avoids frequent real-time recalculations that would generate switching noise during active operations
2Measurement precision
If impedance matching logic frequently recalculates p-code and n-code values to maintain consistent impedance matching, then impedance matching accuracy is improved, but power consumption increases
Solution Approach 1:
The system performs impedance matching recalibration periodically based on freeze signals rather than continuously, significantly reducing power consumption. The control logic monitors temperature and voltage conditions and only triggers recalibration when conditions warrant it, balancing power savings with maintaining adequate impedance matching accuracy
Solution Approach 2:
The impedance matching logic autonomously determines when recalibration is necessary by monitoring operating conditions themselves. The system self-regulates its own calibration needs based on detected temperature and voltage variations, performing calculations only when environmental changes exceed thresholds, thereby minimizing unnecessary power consumption
3Reliability
If impedance matching logic uses a lengthy switching sequence to update code values, then calibration thoroughness is improved, but update time increases
Solution Approach 1:
The patent performs preliminary impedance matching calculations during idle periods or before critical operations. By pre-calculating and storing optimal p-code and n-code values in advance, the system avoids lengthy real-time recalibration sequences, reducing update time while maintaining calibration quality
Solution Approach 2:
The system skips unnecessary calibration steps by using freeze signals to identify when full recalibration is truly needed. When operating conditions are stable, the system rushes through with minimal updates or uses previously stored values, significantly reducing update time while maintaining adequate calibration thoroughness when conditions change
4Speed
If impedance matching logic operates at full output clock frequency, then update speed is improved, but noise and power consumption increase
Solution Approach 1:
The patent uses freeze signals to trigger impedance matching updates only at appropriate moments, rather than operating continuously at full clock frequency. This periodic operation synchronized with stable operating conditions reduces switching noise while maintaining adequate update speed for changing conditions
Solution Approach 2:
The system performs impedance matching calculations in advance during periods when full output clock operation is not critical. By preparing code values beforehand and storing them for later use, the system achieves necessary update speed without continuously operating at high frequency that generates noise
Data Source
AI summary
An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).