Output Buffer Gate Control for Faster Slew Rate at Low Power
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Solution Overview
Problem
Conventional output buffers in source drivers face challenges in enhancing slew rate without increasing power consumption, particularly as display panel resolution and frame rate increase, requiring higher driving capability.
Innovation Solution
The output buffer incorporates an input stage circuit, output stage circuit, rising control circuit, and falling control circuit to dynamically adjust gate control voltages based on input and output voltage comparisons, pulling down or pulling up voltages as necessary to enhance slew rate without increasing tail current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the tail current of the conventional output buffer is increased to enhance the slew rate, then the driving capability is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic control of gate voltages during transient periods. The control circuits dynamically adjust the gate voltages of the output transistors based on whether the output voltage needs to be pulled up or pulled down, enabling the slew rate to be enhanced only when needed rather than maintaining high current continuously.
Solution Approach 2:
The patent changes the gate voltage parameters dynamically during transient periods. By pulling down or pulling up the gate voltages of the output transistors based on the direction of voltage change needed, the effective driving current is optimized without requiring a permanently increased tail current.
2Productivity
If the resolution and frame rate of the display panel are increased, then the display quality is improved, but the charging time for one scan line becomes shorter
Solution Approach 1:
The control circuits prepare by comparing the input voltage with the output voltage to determine the required voltage direction before the actual voltage transition begins. This preliminary comparison enables the gate voltages to be adjusted proactively, reducing the effective charging time.
Solution Approach 2:
The patent employs feedback mechanisms where the output voltage is continuously compared with the input voltage. Based on this feedback, the control circuits adjust the gate voltages to ensure the output voltage transitions in the correct direction with optimal speed, accommodating higher frame rates.
3Speed
If the gate control voltages are dynamically adjusted during transient periods, then the slew rate is enhanced, but the circuit complexity increases
Solution Approach 1:
The patent divides the control function into separate rising control circuit and falling control circuit, each handling specific voltage transition directions. The input stage circuit and output stage circuit are also segmented with distinct responsibilities, making the overall complex system more manageable and implementable.
Solution Approach 2:
The patent introduces control circuits as intermediary elements between the input stage and output stage. These intermediary circuits process the voltage comparison results and generate appropriate gate control signals, simplifying the direct control logic while enabling sophisticated transient optimization.
Data Source
AI summary
An output buffer and an operation method thereof are provided. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage of the output buffer. The output stage circuit correspondingly generates an output voltage of the output buffer according to the first gate control voltage and a second gate control voltage. When the output voltage is to be pulled up, the rising control circuit pulls down the first gate control voltage and the second gate control voltage during a first transient period. When the output voltage is to be pulled down, the falling control circuit pulls up the first gate control voltage and the second gate control voltage during a second transient period.