Output Buffer Impedance Calibration Without Active-State Noise
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Solution Overview
Problem
In semiconductor devices like DRAM, accurate impedance adjustment of output buffers is challenging due to the dependence on external clock cycles, leading to potential noise in input/output signals during calibration periods, especially at higher frequencies and due to process variations.
Innovation Solution
A method where the impedance adjustment circuit discontinues adjustments during active states of the circuit, particularly when receiving read or write commands, and supplies driver codes only after the circuit transitions to a deactivated state, ensuring impedance adjustments are synchronized with internal clock signals and preventing noise generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If impedance adjustment is performed using external clock cycles, then calibration can be completed, but calibration period decreases when external clock frequency increases leading to insufficient calibration time
Solution Approach 1:
The patent segments the calibration process from the operational process by using separate internal clock cycles dedicated to impedance adjustment. The internal clock is independent from the external data transfer clock, allowing calibration operations to be performed in isolated time segments without being constrained by external clock frequency.
Solution Approach 2:
The patent performs impedance calibration as a preliminary action before normal data transfer operations begin. By completing the calibration phase using internal clock cycles beforehand, the system ensures that impedance adjustment is finished before high-speed external operations start, preventing interference between calibration and data transfer.
2Measurement precision
If calibration is performed continuously, then impedance adjustment can be completed, but noise is generated in input/output signals during active operations
Solution Approach 1:
The patent extracts the calibration function from the operational timeline by dedicating specific calibration periods separate from active data transfer periods. During these extracted calibration periods, the internal clock performs impedance adjustment while the external interface remains inactive or in a high-impedance state, preventing noise injection into active signal lines.
Solution Approach 2:
The patent implements periodic calibration cycles where impedance adjustment is performed in discrete time intervals rather than continuously. The internal clock generates periodic calibration pulses that activate the calibration circuit only during designated periods, while normal data transfer operations proceed uninterrupted during operational periods.
3Measurement precision
If calibration period is extended to ensure accuracy, then impedance adjustment precision improves, but data transfer efficiency decreases
Solution Approach 1:
The patent segments total operation time into distinct calibration segments and data transfer segments. The internal clock manages calibration segments with sufficient duration for accurate impedance adjustment, while external clock manages data transfer segments for high-speed communication. This segmentation allows each function to operate optimally without compromising the other.
Solution Approach 2:
The internal clock acts as an intermediary mechanism that handles calibration operations independently from the external clock system. This intermediary allows calibration to proceed at its own pace using internal timing resources, preventing calibration duration from directly impacting external data transfer timing and efficiency.
Data Source
AI summary
A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.